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Cyclone V remote update failed by nStatus negative pulse.

January 18, 2018, 5:53 am
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Hello,

I am using cyclone V with S25FL064 flash.
I generate a sof with rsu for both factory image and user image, and coverted all of them into .flash. The address of two apps is just after the sof.
Address arrangement(memory map):
Factory:
0x000000 sof
0x17xxxx factory image
User:
0x200000 sof
0x37xxxx User image
All of the .flash are burned into S25FL064 with nios2-flash-programmer.
After resetting, the factory image boots well and starts to reconfig to user image, but it fails to reconfig to the user image and reboots again.
From the scope, I capture a negative pulse on nStatus, at the same time conf_done also goes low (keep low around 600ms, then goes high. I think it because the reboot succeeds), nothing changes on nConfig.
After reboot, the rsu status is read as 0x04 which indicates nStatus fail.
Could anyone help? I do very appreciate for any proposal.

Best Regards
hdai
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Cyclone V remote update failed by nStatus negative pulse.

January 18, 2018, 6:35 am
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Cyclone V remote update failed by nStatus negative pulse.

Hello,

I am using cyclone V with S25FL064 flash.
I generate a sof with rsu for both factory image and user image, and coverted all of them into .flash. The address of two apps is just after the sof.
Address arrangement(memory map):
Factory:
0x000000 sof
0x17xxxx factory image
User:
0x200000 sof
0x37xxxx User image
All of the .flash are burned into S25FL064 with nios2-flash-programmer.
After resetting, the factory image boots well and starts to reconfig to user image, but it fails to reconfig to the user image and reboots again.
From the scope, I capture a negative pulse on nStatus, at the same time conf_done also goes low (keep low around 600ms, then goes high. I think it because the reboot succeeds), nothing changes on nConfig.
After reboot, the rsu status is read as 0x04 which indicates nStatus fail.
Could anyone help? I do very appreciate for any proposal.

Best Regards
hdai
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MAX 10 ADC Simulation

January 18, 2018, 7:03 am
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Hello,

I'm using the MAX 10 Development Board and want to simulate the ADC (Modular Dual ADC IP core).

According to the manual the ADC samples are stored in the sample storage core and after receiving a block of ADC samples it asserts an Interrupt Signal. The samples can retrieved through the Avalon-MM slave interface.
What i want to do is, to post-process the received ADC values. Therefore i will wait for the Interrupt and then read the values out of the ADC Sample Register.

So far, i created a Modular Dual ADC IP core and its simulation model out of the Platform Designer (Qsys) see attachment.
I created a simple testbench where i just have a clock generator.

The simulation failed with many errors like:
"Instantiation of 'ADC_ADC_control_internal' failed. The design unit was not found.." and similar errors.
"Port "configupdate" of entity "adc_pll" is not in the component being instantiated."
I don't know why it is missing because i generated it from Qsys and didn't write the codes by my own.

Can someone help/give me an advise how to approach this task?

Best regards!
Attached Images
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Get BAR contents from PCIe ipcore application side

January 18, 2018, 8:15 am
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Hi all,

I want to get the RC (host) give access to the memory on the FPGA board via PCIe. In order to do this the application code running in the FPGA needs to know the contents of the BAR used to access that memory. This is needed because PCIe transaction contains the mapped address as seen from the host. To calculate the memory address as seen by the FPGA I need to subtract the BAR contents from the address in the transaction.

I've googled around and have read the PCIe core documentation but did not find a good way to read the BARs. There is the LMI but the documentation says that one should not use it except for writing AER stuff.

If reading the BAR is complicated (as via LMI) I would also need a signal that the BAR has changed, because the host may change it at any time and to correctly process a transaction I need the actual value. Reading the BAR via LMI for every transaction does not look reasonable.

So how is this supposed to be done?

Thanks,
harti
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FPGA Bridge enabled, but signal tap shows data is zeros

January 18, 2018, 10:55 am
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Thanks in Advanced.

Previously I have done the same thing on a Macnica Sodia board but used the FPGA DDR memory to do the same thing -- so I HAVE VERIFIED that my firmware works as advertised.
Currently - I want to use HPS DDR to reduce the DDR chips needed for our custom PCB so ... I am

working on a Macnica Helio board took the Q14.1 Golden Design and added my IPs then - I have used Q17.1 bsp-editor and associated commands to generate the u-boot and preloader.

If necessary I can provide those instructions.

I am using kernel 4.1.33-ltsi with some extra features enabled.

At first my *.dtb file was not correctly resetting the bridge, but subsequently I changed the *.dtb (and from another post I matched it to the *.dtb of the kernel).

AND I can see during boot
[ 2.272449] fpga_manager fpga0: Altera SOCFPGA FPGA Manager registered
[ 2.279599] altera_hps2fpga_bridge sopc@0:fpgabridge@0: fpga bridge [hps2fpga] registered
[ 2.288011] altera_hps2fpga_bridge sopc@0:fpgabridge@1: fpga bridge [lwhps2fpga] registered
[ 2.296481] altera_hps2fpga_bridge sopc@0:fpgabridge@2: fpga bridge [fpga2hps] registered


And I can see everything in /sys/class/fpga-bridge/


I HAVE SIGNAL TAP SET UP TO SEE THE avs and avm signals -->
I have a device driver that has a kernel buffer of known data and I give the firmware that start address to read from BUT I can see all the correct bus signals but the data read from the address IS NOT THE EXPECTED DATA IT IS ZERO !!!

What am I missing?
IS MY KERNEL NOT IN SYNC??
Also, how do I know the address of fpgabridge@0, @1, @2 - to verify that they match properly (it used to be at boot you saw the actual addresses).

Any help/ideas will be greatly appreciated !!!
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Using IOWR/IOWR_32DIRECT macro to transfer char array to SDRAM

January 18, 2018, 11:21 am
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Hello,

I'm new to both C and using NIOS and I can't seem to figure out how to use the IOWR_32DIRECT macro. I'm trying to transfer a 2D unsigned char array (rx_frame) from on-chip memory to the SDRAM, 32 bits at a time. The data bus is 32 bits on both the on-chip memory and SDRAM controller.

Here's what I have:

for (i = 0; i < length; i++) {
IOWR_32DIRECT(4*i, 0, rx_frame[0][4*i]);
}

The result is that I get rx_frame[0][0] at location 0x0 but locations 0x1,0x2 and 0x3 are 0.
Then I get rx_frame[0][4] at location 0x4 but locations 0x5, 0x6 and 0x7 are 0.
Then I get rx_frame[0][8] at location 0x8 but locations 0x9, 0xA and 0xB are 0.
Then I get rx_frame[0][12] at location 0xC but locations 0xD, 0xE and 0xF are 0. etc...

Any idea what I'm doing wrong and what I should be doing ?
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RTL module crashes computer

January 18, 2018, 11:49 am
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Hi,

I have a purely combinatorial RTL module as part of my OpenCL pipeline. The design compiles without problems or warnings. However, when executing the program, it first stalls for a few minutes, then the entire computer hangs and requires a manual restart. I can't make sense of this because:

- Simulating the verilog itself works.
- The design has no internal states and it's stall free with a fixed (0) latency.
- Just using a simpler (but also combinatorial) design without touching any of the other code does not show the problem.
- Status flags iready/oready/ivalid/ovalid are not used (just routed through)
- The output of the RTL module just gets transferred back to the host (no further computation depends on it).

I'm using the 16.1 SDK with the DE5a-net board. Any suggestions on how to debug this would be appreciated!

Thanks,
Hanno
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Fix System ID Properties in Nios II

January 18, 2018, 10:44 am
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When I go under Run configuration for my Nios system, It can not locate any of the system ID Properties. Does anyone know a way to fix this?
I have inspected all of my Platform Designer/Qsys and my main Quartus Project. All of them successfully build, generate, and compile with no errors. I am assuming this is some kind of memory mapping issue, but the addresses in system.h seem correct. (java.lang.Exception) is the error that it displays when I try to run my system on the board (Max10). I did push the .sof file onto the chip ahead of time.
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all of a sudden ...Error: Compiler Error, not able to generate hardware

January 18, 2018, 11:56 am
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Hi, now I got a problem and don't know where to look at....

It says:
Error: Compiler Error, not able to generate hardware

here are some details..please have a look, and tell me what to do or where to look at...

..
Terasic DE5Net OpenCL BSP 16.1 / 8 Core 16GB Host,Windows 10 x64

I can't combile my OpenCL.cl until end,
Hardware, Software, Drivers ans Path Variables ...seems ok...but you never know

I could need some advice an any clue :)

hello_world and vector_add comiled OK
my first own hello world worked fine

Code:
E:\altera\OpenCL>aoc --list-boards
Board list:
  de5net_a7
Code:
E:\altera\OpenCL>aocl diagnose acl0
aocl diagnose: Running diagnostic from E:\altera\16.1\hld\board\de5net16.1/windows64/libexec


Verified that the kernel mode driver is installed on the host machine.


Using platform: Altera SDK for OpenCL
Using Device with name: de5net_a7 : Terasic's Preferred Board
Using Device from vendor: Terasic Corporation
clGetDeviceInfo CL_DEVICE_GLOBAL_MEM_SIZE = 4294967296
clGetDeviceInfo CL_DEVICE_MAX_MEM_ALLOC_SIZE = 4293918720
Memory consumed for internal use = 1048576
Actual maximum buffer size = 4293918720 bytes
Writing 4095 MB to global memory ...
Write speed: 1281.97 MB/s [1270.64 -> 1292.75]
Reading and verifying 4095 MB from global memory ...
Read speed: 1440.19 MB/s [1438.94 -> 1440.95]
Successfully wrote and readback 4095 MB buffer


Transferring 8192 KBs in 16 512 KB blocks ... 882.76 MB/s
Transferring 8192 KBs in 8 1024 KB blocks ... 1010.60 MB/s
Transferring 8192 KBs in 4 2048 KB blocks ... 1224.59 MB/s
Transferring 8192 KBs in 2 4096 KB blocks ... 1320.80 MB/s
Transferring 8192 KBs in 1 8192 KB blocks ... 1342.77 MB/s


PCIe Gen2.0 peak speed: 500MB/s/lane


Writing 8192 KBs with block size (in bytes) below:


Block_Size Avg    Max    Min    End-End (MB/s)
  524288 688.91 727.15 584.17 680.89
 1048576 896.36 928.95 794.87 888.06
 2097152 1060.30 1090.68 1040.20 1055.01
 4194304 1133.18 1140.87 1125.60 1131.85
 8388608 1155.83 1155.83 1155.83 1155.83


Reading 8192 KBs with block size (in bytes) below:


Block_Size Avg    Max    Min    End-End (MB/s)
  524288 791.50 882.76 578.99 780.42
 1048576 916.96 1010.60 829.17 911.15
 2097152 1188.68 1224.59 1109.91 1183.89
 4194304 1316.73 1320.80 1312.69 1312.16
 8388608 1342.77 1342.77 1342.77 1342.77


Write top speed = 1155.83 MB/s
Read top speed = 1342.77 MB/s
Throughput = 1249.30 MB/s


DIAGNOSTIC_PASSED
Code:

E:\altera\OpenCL>aoc --version
Altera SDK for OpenCL, 64-Bit Offline Compiler
Version 16.0.2 Build 222
Copyright (C) 2016 Altera Corporation
Code:
E:\altera\OpenCL>aoc -v kernel.cl
aoc: Environment checks are completed successfully.
You are now compiling the full flow!!
aoc: Selected default target board de5net_a7
aoc: Running OpenCL parser....
aoc: OpenCL parser completed successfully.
aoc: Compiling....
aoc: Linking with IP library ...
+--------------------------------------------------------------------+
; Estimated Resource Usage Summary                                  ;
+----------------------------------------+---------------------------+
; Resource                              + Usage                    ;
+----------------------------------------+---------------------------+
; Logic utilization                      ;  43%                    ;
; ALUTs                                  ;  24%                    ;
; Dedicated logic registers              ;  20%                    ;
; Memory blocks                          ;  30%                    ;
; DSP blocks                            ;    6%                    ;
+----------------------------------------+---------------------------;

aoc: First stage compilation completed successfully.
Error: Compiler Error, not able to generate hardware
qoc 1'st stage ..OK..1 CPU Core ~ about 1 min
quertus_map ..OK..8 CPU Cores ~ about 7GB RAM 30 min
quertus_cdb ..OK..1 CPU Core ~ about 2GB RAM 10 min
quertus_fit ..ERROR..1 CPU Core ~ about 2GB RAM 5 min

kernel_log
Code:
2018.01.18.19:26:10 Info: system: Done "system" with 170 modules, 550 files
quertus_sh_compile
Code:
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 665 warnings
Info: Peak virtual memory: 8145 megabytes
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3rd party boot flash memory in ASx4

January 18, 2018, 12:10 pm
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Hi,

Need guidance on using a 3rd party configuration NOR flash for Cyclone V. the configuration scheme is ASx4.
Altera and all other major vendors were stoped the production of low density NOR flash devices which forced us to use a 3rd party vendor e.g ISSI, Macronix and etc.
These vendor's Flash devices are not compatible with the Altera devices. there are differences in dummy cycles, device ID or some bits in the status register.
The solution needs to involve a reconfiguration using NIOS soft processors to reconfigure the flash device before loading the firmware.
I don't know how to do this.
Can anyone get me a step by step guidance?

Thanks
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all of a sudden..Error: Compiler Error, not able to generate hardware

January 18, 2018, 12:25 pm
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Hi, now I got a problem and don't know where to look at....


It says:
Error: Compiler Error, not able to generate hardware


here are some details..please have a look, and tell me what to do or where to look at...


..
Terasic DE5Net OpenCL BSP 16.1 / 8 Core 16GB Host,Windows 10 x64


I can't combile my OpenCL.cl until end,
Hardware, Software, Drivers ans Path Variables ...seems ok...but you never know


I could need some advice an any clue


hello_world and vector_add comiled OK
my first own hello world worked fine


Code:
E:\altera\OpenCL>aoc --list-boards
Board list:
  de5net_a7

Code:
E:\altera\OpenCL>aocl diagnose acl0
aocl diagnose: Running diagnostic from E:\altera\16.1\hld\board\de5net16.1/windows64/libexec




Verified that the kernel mode driver is installed on the host machine.




Using platform: Altera SDK for OpenCL
Using Device with name: de5net_a7 : Terasic's Preferred Board
Using Device from vendor: Terasic Corporation
clGetDeviceInfo CL_DEVICE_GLOBAL_MEM_SIZE = 4294967296
clGetDeviceInfo CL_DEVICE_MAX_MEM_ALLOC_SIZE = 4293918720
Memory consumed for internal use = 1048576
Actual maximum buffer size = 4293918720 bytes
Writing 4095 MB to global memory ...
Write speed: 1281.97 MB/s [1270.64 -> 1292.75]
Reading and verifying 4095 MB from global memory ...
Read speed: 1440.19 MB/s [1438.94 -> 1440.95]
Successfully wrote and readback 4095 MB buffer




Transferring 8192 KBs in 16 512 KB blocks ... 882.76 MB/s
Transferring 8192 KBs in 8 1024 KB blocks ... 1010.60 MB/s
Transferring 8192 KBs in 4 2048 KB blocks ... 1224.59 MB/s
Transferring 8192 KBs in 2 4096 KB blocks ... 1320.80 MB/s
Transferring 8192 KBs in 1 8192 KB blocks ... 1342.77 MB/s




PCIe Gen2.0 peak speed: 500MB/s/lane




Writing 8192 KBs with block size (in bytes) below:




Block_Size Avg    Max    Min    End-End (MB/s)
  524288 688.91 727.15 584.17 680.89
 1048576 896.36 928.95 794.87 888.06
 2097152 1060.30 1090.68 1040.20 1055.01
 4194304 1133.18 1140.87 1125.60 1131.85
 8388608 1155.83 1155.83 1155.83 1155.83




Reading 8192 KBs with block size (in bytes) below:




Block_Size Avg    Max    Min    End-End (MB/s)
  524288 791.50 882.76 578.99 780.42
 1048576 916.96 1010.60 829.17 911.15
 2097152 1188.68 1224.59 1109.91 1183.89
 4194304 1316.73 1320.80 1312.69 1312.16
 8388608 1342.77 1342.77 1342.77 1342.77




Write top speed = 1155.83 MB/s
Read top speed = 1342.77 MB/s
Throughput = 1249.30 MB/s




DIAGNOSTIC_PASSED

Code:


E:\altera\OpenCL>aoc --version
Altera SDK for OpenCL, 64-Bit Offline Compiler
Version 16.0.2 Build 222
Copyright (C) 2016 Altera Corporation

Code:
E:\altera\OpenCL>aoc -v kernel.cl
aoc: Environment checks are completed successfully.
You are now compiling the full flow!!
aoc: Selected default target board de5net_a7
aoc: Running OpenCL parser....
aoc: OpenCL parser completed successfully.
aoc: Compiling....
aoc: Linking with IP library ...
+--------------------------------------------------------------------+
; Estimated Resource Usage Summary                                  ;
+----------------------------------------+---------------------------+
; Resource                              + Usage                    ;
+----------------------------------------+---------------------------+
; Logic utilization                      ;  43%                    ;
; ALUTs                                  ;  24%                    ;
; Dedicated logic registers              ;  20%                    ;
; Memory blocks                          ;  30%                    ;
; DSP blocks                            ;    6%                    ;
+----------------------------------------+---------------------------;


aoc: First stage compilation completed successfully.
Error: Compiler Error, not able to generate hardware

qoc 1'st stage ..OK..1 CPU Core ~ about 1 min
quertus_map ..OK..8 CPU Cores ~ about 7GB RAM 30 min
quertus_cdb ..OK..1 CPU Core ~ about 2GB RAM 10 min
quertus_fit ..ERROR..1 CPU Core ~ about 2GB RAM 5 min


kernel_log
Code:
2018.01.18.19:26:10 Info: system: Done "system" with 170 modules, 550 files

quertus_sh_compile
Code:
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 665 warnings
Info: Peak virtual memory: 8145 megabytes
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Passive Serial vs. JTAG programming

January 18, 2018, 7:08 pm
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I encountered a very puzzling problem. The FPGA code is compiled and downloaded to the Cyclone chip with JTAG, then the Cyclone hardware system is verified to be functional as expected. The same FPGA code is then converted to be an RBF file, then this raw image file is imported and downloaded from a processor using the passive serial configuration. The Cyclone chip could self boot, the logic modules within the chip is still functioning through SignalTap, but the FPGA lost the communication to the processor. While using the JTAG, there is no such issue as losing the communication.

Have you encountered situations like this before? Any suggestions or solutions?
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dac5682z hsmc EP4SG530KH

January 18, 2018, 11:03 pm
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I want to take FPGA and dac5682z through the HSMC link together to set the DAC sdenb to end, but did not find a suitable pin, encountered the problem is the lowest level of HSMC pin 2.5V side, DAC pin up to 2.3V, the typical value is 1.8, want to ask, the available sdenb pin. 7777 is rtl viewer
Attached Images
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fast forward tming closure for Stratix

January 18, 2018, 11:32 pm
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Hi,

I am using Hyper Optimization for Stratix design and on the fast forward optimization recommendations i don't get any info due to something called 'Retiming Dependency loop' .I am checking the document at https://www.altera.com/documentation...270893021.html but i can't see any topic on this , just for generic loops. How could i solve this problem in order to get some recommendations?
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DE10 Nano J8 2x5 pins

January 18, 2018, 11:55 pm
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Hello,

What are the pins for the J8 2x5 header on the DE10-NANO? The manual says

"In addition, the DE10-Nano has one external JTAG Header (J8) reserved for users toconnect to JTAG chain of the DE10-Nano via external blaster. The J8 header is not installed,
so users need to solder a 2.54mm 2x7 male pin header if it is necessary."

J8 is actually 2x5. Nowhere is there a description of the 10 pins. Does anyone know what the pins are?

Thanks
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Cannot meet timing constraints for LVDS I/O at 800 Mbps on Cyclone V SX

January 19, 2018, 12:07 am
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Hi!
I have been badly struggling for 8-10 days trying to meet the timing constraints for LVDS I/O at 640Mbps. I am trying to use SERDES for LVDS data (2 lane) from 16 bit ADC (AD9563) to the FPGA (5CSXFC6D6F31C6) at 640Mbps.
There is always input setup and hold violations. I have tried what all I could do. I am assuming that the 16 bit ADC is sampled at 80MSPS and hence LVDS rate on each of the 2 lanes will be 640Mbps. Also the ADC_0_DCO clock out from the ADC is exactly at the centre of the data (data window is 1.5625ns). Thus can I assume that Tco of the external device which is the ADC is 1.5625/2 (= 0.78125 ns) ?

My project is very simple. I am using ALTLVDS_RX with 640Mbps data rate, 320MHz inclock, serialization factor of 8. I learnt from some forum about constraining and got hold of some example on constraining DDR inputs and the same has been implemented in my design. The constraints are as below:

set input_clock ADC_0_DCO; # Name of input clock
set trco_max 0.781; # Maximum clock to output delay from rising edge (external device)
set trco_min 0.781; # Minimum clock to output delay from rising edge (external device)
set tfco_max 0.781; # Maximum clock to output delay from falling edge (external device)
set tfco_min 0.781; # Minimum clock to output delay from falling edge (external device)
set trce_dly_max 0.781; # Maximum board trace delay
set trce_dly_min 0.781; # Minimum board trace delay
set input_ports { Datain[0] }; # List of input ports

# Input Delay Constraint
set_input_delay -clock $input_clock -max [expr $trco_max + $trce_dly_max] [get_ports $input_ports];
set_input_delay -clock $input_clock -min [expr $trco_min + $trce_dly_min] [get_ports $input_ports];
set_input_delay -clock $input_clock -max [expr $tfco_max + $trce_dly_max] [get_ports $input_ports] -clock_fall -add_delay;
set_input_delay -clock $input_clock -min [expr $tfco_min + $trce_dly_min] [get_ports $input_ports] -clock_fall -add_delay;

I have attached the files for reference.

Can pl some help and meet the timing... Thanks in advance

best wishes,
Attached Files
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voltage level of GPIO pins of Cyclone 10 GX

January 19, 2018, 12:15 am
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Hi all,

I have recently encountered a problem while working with a design that has alot (4 to 5) 3.3 v I/O peripherals to be interfaced with Cyclone 10 GX FPGA. The design challenge is the FPGA has just 48 pins (1 I/O ) bank that supports I/O standards upto 3.3 V ,rest all pins among the other 280+ pins are supporting standards only upto 1.8 V .

One of the 3.3V peripherals itself have around 60-70 I/O pins , using a voltage translator chips might introduce skew between the signals...as voltage translator chips generally only support max upto 32 signals.

If anyone can suggest a workaround to effectively use Cyclone 10 GX smoothly.

Thanks,
fpga993
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Simulation Program for DE1-SoC board

January 19, 2018, 5:34 am
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I have a DE1-SoC board which i can work on via Intel FPGA monitor program but I would like to perform simulations of my assembly code without connecting the board.

For this purpose, is there any simulation application of DE1-SoC board ?
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Is this already maximally pipelined ... anything I can do to speed this up?

January 19, 2018, 7:21 am
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According to .sta.rpt Fmax for this is 307 MHz which is less than 50% of the datasheet listed max speed...

wbr Kusti

Code:

always @(posedge sys_clk) begin
Code:
    if (($signed({1'd0, e}) | (counter >= $signed({1'd0, 1'd0})))) begin
        product <= (a * b);
        accum_product <= (accum_product + product);
        accum_in_a <= (accum_in_a + a);
        accum_in_b <= (accum_in_b + b);
        product_accum_in_a_and_b <= (accum_in_a * accum_in_b);
    end
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Error (12097): Can't find port "reset" in OpenCore Plus entity "alt_vip_cvo_core".

January 19, 2018, 8:43 am
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Hi All,

We are using HDMI-FMC kit from Terasic and trying to bring-up loop-back demo with Arria 10 kit. They provide Loop-back demo design with HDMI-FMC kit and I am trying to regenerate the demo bit-stream on Quartus 16.0 and I get below error. I am not sure what the issue is. I have tried loading the design on Quartus 15.1 and also on Quartus 17.0, but I get the same error on all the versions of the software. I am able to open Qsys file and regenerate HDL files without any issues. I contacted the Terasic tech-support, they claims it's license issue; however, I doubt that because I looked at all the warning and error messages and I do not see any warnings or error messages related to license. Has anyone seen this kind of issue before?

Error (12097): Can't find port "reset" in OpenCore Plus entity "alt_vip_cvo_core". -- OpenCore Plus specification file is invalid

Regards,
Hanumanth
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