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time limited sof file generation

February 16, 2018, 6:02 am
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Hi,

I observed the following behaviour using Quartus 17.0.

When i start to add my own custom IP into the qsys, then the time_limited sof file is generated and the behaviour of my eclipse program is not the same anymore.

1. Where can I find the evaluation timeout?
2. Why is there a different sof(time limited) file generated once I add my own IP?

3. There seems to be a functional difference between a time_limited_sof and the .sof.
I do the following. I receive over the UART IP core some data values and loop them back in the NIOS-II using a small c-program.

This is working fine when I do not use my own IP core in the design, as soon as I include my own IP core the time_limited_sof is generated, but from this point of time the loopback on the UART is not working anymore.

In both cases I use the same c-program, sure I have different system.h files due to the fact that one my IP core is in the design, once it not included in the design. My c-program does not access my IP core instance, so the software
is independent from the usage of my IP core.

Any idea where I could look for understanding this behaviour ?



Thanks in advance!
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Arria 10 GX Dev Board: USB-Blaster plugged into JTAG port can't access JTAG chain?

February 16, 2018, 9:27 am
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My Arria 10 GX dev. board works fine as long as I am accessing the JTAG chain using the USB port on the front end of the board (where the micro-USB cable plugs in). But, if I try to use a USB-Blaster plugged into the JTAG port (J17) I get the error "can't access JTAG chain." I've tried both orientations with the same results. I've checked the switches on SW4 and they are still in the default setting. Is there another switch I need to toggle?
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FIFO Works fine on EDAPlayground but not Quartus

February 16, 2018, 10:18 am
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All,
The following code works fine and as expected on EDAPlayground, but Quartus has an issue with it.
I get the ERROR 10028 Can't resolve multiple constant drivers for nets w_addr and r_addr.

I am treating w_addr and r_addr as a temporary variable that can have a value 0 to 31, (5-bits)

Any ideas?
Thanks,
Keith


Code:
//////////////////////////////////////////////////////////////////////
//================================================================
// FIFO test in an array specfic for HiDS
// set up for Dual clocks
//      one to Write
//      one to Read
// also will need to have 2 data busses
//      Data IN
//      Data OUT
// Extras
//      nReset -- CLR on LO
//      Empty -- HI indicates empty
module DFIFO_array(D_Out, Empty, D_In, wrclk, rdclk, nrst);
 
  output [WIDE-1:0] D_Out;
//output [40:0] D_Out;
  output Empty;

  reg [WIDE-1:0] D_Out;
//reg [40:0] D_Out;
     
  input [WIDE-1:0] D_In;
//input [40:0] D_In;
 
  input wrclk;
  input rdclk;
  input nrst;
 
  //
  // DFIFO for 64 Channel SAM 41 x 32
  // EFIFO for 64 Channel SAM 10 x 64
  parameter WIDE = 41;
  parameter DEEP = 32;
 
  // this should give us a FIFO of 41 bits Wide by 32 words deep
  // 9-bit counter in MSB bits 32:41
  // 32-bit channel representation in 0:31
  //
  //
  reg [WIDE-1:0] addr[DEEP-1:0];
//reg [40:0] addr[32:0];
  reg [4:0] w_addr;
  reg [4:0] r_addr;
 
  always @ (posedge wrclk)
    begin
      addr[w_addr] <= D_In;
      w_addr <= w_addr + 1;
    end
 
  always @ (posedge rdclk)
    begin
      r_addr <= r_addr + 1;
      D_Out <= addr[r_addr];
    end
 
  always @ (nrst)
    begin
      if (!nrst)
        begin
          w_addr <= 0;
          r_addr <= 0;
        end
    end
 
  assign Empty = (w_addr == r_addr);
 
endmodule

/////////////////////////////////////////////////////////////
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FPGA (Cyclone IV E) new project after a long break

February 16, 2018, 5:11 pm
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Hi everyone! I am new on this forum :)

I have a problem.

Once (quite a long time ago) I had a module from embedded systems and FPGAs during my studies but unfortunately I do not remember anything anymore.

Now, however, I must go back to FPGA. I installed Quartus.

I tested a little. In the case of very simple projects, I would probably be able to do something.

What I want to do, however, has one element that goes beyond what I did even in college. I never referred to memory in Quartus (or at least I do not remember). I intend to use Cyclone IV E in my project. Someone could tell me how to use memory in Quartus projects?

I mean the elementary functions "only read to one address" or "only write to one address". There are many possibilities at Quartus. There are a lot of blocks for these functions <- most of the extended ones.

Anyone could advise something?

Thank you so much for help!
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help with TOP I/O management

February 17, 2018, 5:01 am
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Hello,<br>
<br>
I am student who recently got my hands on DE10-nano. Up until now I was always working with Artix-7, Xilinx board. What I am trying to do is to migrate some of my projects to Intel-Quartus. What I am now fighting is an assignments of TOP IO. In Vivado(overall Xilinx products) I had constraints, where there was a IO assignments available, so-called master.xdc files. Here I will post what I am used to work with and I would like to ask someone, if could tell me how to get the same result here in Quartus.<br>
<br>
library IEEE;<br>
use IEEE.STD_LOGIC_1164.ALL;<br>
use IEEE.STD_LOGIC_UNSIGNED.ALL;<br>
use ieee.fixed_pkg.all;<br>
<br>
<br>
entity TOP is<br>
Port (<br>
<br>
<br>
JA1 : out STD_LOGIC; -- pwm<br>
btnL : in STD_LOGIC; --debouncerL for state_machine - reset<br>
clk : in STD_LOGIC<br>
);<br>
end TOP;<br>
<br>
With this I can take oscilloscope and see the PWM if I connect it to JA1 pin.<br>
<br>
In quartus I can't find how to assign this output lets say to pin GPIO_0 D1, because I really don't know how to declare it.<br>
Can anyone please tell me how does this work in quartus. I have never been working with it and I think I am stuck with the Vivado way of doing thing and can't comprehend how does it work here.<br>
<br>
Thank you.<br>
IK
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Hardware not working as intended

February 17, 2018, 7:43 am
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Hi all,

I am stuck with a problem since many days and I am unable to debug.
Any help is appreciated.

I have a OpenCL FPGA kernel which is a part of larger program.
it has something like
if(tid <numVertices{
do-some floating point ops
}

In the host code i want to call the function in a loop after setting arguments;
for(int i=0;i<100;i++){
// some operations

err = clEnqueueNDRangeKernel(command_queue, kernel[3], 1, NULL,
workSize_4, localWorkSize_4, 0, NULL, &clContext.events[1]);
clFinish(command_queue);
ExitError(checkErr(err, "Failed to execute kernel4!"));

//some more operations
}

---------------
Everything works fine (as intended) in emulation and also on CPU.
The problem comes when I execute it on Altera FPGA (both Intel Harp and Nallatech) with the generated respective aocx files
When the numVertices is "even"(multiple of 2), the code exits normally and the output is as intended, but when numVertices is "odd" the process enters into sleep state and stays there forever. No error is shown.
When I try to debug using GDB, SIG INT 44 is shown. I tried to use pstack but was not able to find the exact problem.


Thank you.

Regards,
Sharat



The kernel (not yest optimized) which fails to execute is as shown below:
----------------------------
#define KNOB_COMPUTE_UNITS_1 1
#define KNOB_SIMD_1 1
#define KNOB_NUM_WORK_ITEMS_1 256
/* kernel 4*/
#ifdef ALTERA_CL
__attribute__ ((reqd_work_group_size(KNOB_NUM_WORK_ITEMS_1,1,1)) )
__attribute__ ((num_simd_work_items(KNOB_SIMD_1)))
__attribute__ ((num_compute_units(KNOB_COMPUTE_UNITS_1)))
#endif
__kernel void kernel4(__global double* restrict newpr,
__global double* restrict w,
unsigned int numVertices
) { //numVertices private variable
__private size_t tid = get_global_id(0);

if(tid< numVertices){
newpr[tid] += w[0] * (1/(double)numVertices);
}
}
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C9555E: ARM DS-5 Failed to check out an (existing) license.

February 17, 2018, 12:03 pm
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Hello forum members,

I am trying to compile a bare metal "hello world" application (https://www.altera.com/documentation...o1424282721112)
After installing a 30-day evaluation license (today) I see in the "view and edit licenses window"
A checked (green check) "DS-5 Ultimate Edition (30-day evaluation).lic".
The link to the license file and the file were automatically generated when I appied for a license from the Arm server.
So the licensing seems ok,

The "About window" of Arm DS-5 v5.27.1 Ultimate Edition (Evaluation) is shows:
Full product installation (win32, x86_64)
Java HotSpot(TM) 64-Bit Server VM, version: 1.8.0_4
So the licensing seems ok again,

However compiling my appication I get: "C9555E failed to check out a license"
In the "Problems" window?
Does anybody have any idea what I could do to solve the error?

Best regards,
Johi.
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EMIF DDR4 using ECC: ctrl_ecc_user_interrupt signal's timing, information?

February 17, 2018, 3:34 pm
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Dear Altera's board users,

I am using an EMIF for a DDR4 that has a 72 bits DQ, this allows me to use ECC verification and auto correction.
I checked: Enable Error Detection and Correction Logic and Enable auto correction in Qsys.

One signal appeared called ctrl_ecc_user_interrupt, an output of 1 bit size and I can see the very small description in the External memory interface Volume 1 at page 326 at Table 7-45.

Nevertheless I don't see any timing. When this signal is used? What the level of activation ? How long? 1clock? which one? Avalon MM's clock or DDR's refclock? Synchronous with readdatavalid? or instead of readdatavalid? ...

I am asking that because using Signaltap for an Arria10 chip, I see this signal staying high all the time but in the simulation with the example design and traffic generator, the signal stays low all the time. (Modelsim DE 10.7)

How can I know in details what does this signal?

Thank you,
Regards,
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Problem to creat SD-Card for the DE0-Nano SoC

February 18, 2018, 4:33 am
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Hi there, I'm a beginner in the field of Embedded Linux of SoC.

At the first, I tried to creat a SD-Card for a DE0-Nano-SoC Development Board with the Image "DE0-Nano_SoC_UP_Linux" from the Altera Website (DE0-Nano-SoC Linux SD Card Image) and the Win32 Disk Imager - 1.0.
After inserting my created SD into the Board, the LED for FPGA-Config is on after few seconds, but the Linux does not boot. I also tried it with different MSEL-Conigurations, but it does not boot.
Does anyone have an idea what I did wrong?

Link to the Altera Image: https://www.altera.com/support/train...r-systems.html
I prefer this image because the Desktop based Ubuntu and the included features and apps.

I tried it also with another Image with Linux Console, and than it works! The Linux boot after a few seconds.

I'm very happy about any answers.
Kind Regards.
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Error (12006): Node instance "zzzzz" instantiates undefined entity "zzzzz"

February 18, 2018, 9:21 pm
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hey guys....
i m new in to use altera...
i had generate code using qsys and when i am going to compiling my design it will showing some errors...like




i had added this files in my setting -> files



plz can anyone help me to solve this problem.......
Attached Images
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Niosll vga output

February 18, 2018, 11:21 pm
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Hi all,

I am designing a Nios ll classic processor based SOC for DE2-115 , when i studied its .v (soc instantiation) file i noticed that vga controller out ports i.e

output wire [7:0] vga_controller_ext_R, // .R
output wire [7:0] vga_controller_ext_G, // .G
output wire [7:0] vga_controller_ext_B // .B
);

are all 8-bit ???? this is wrong it should be 10-bit as per DE2-115 vga DACs .

i used the Altera UP IPs for creating all components in Quartus prime ver 16.0 .

And i dont see any option to change the width of RGB output on vga controller ???

Any one any idea whats wrong here ???

Regards
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On-board usb blaster configuration files for MAX 10 10M50 Evaluation Kit

February 19, 2018, 12:34 am
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Dear all,

We want to reuse deign files of the MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R):
https://www.altera.com/products/boar...valuation.html

I need to know how to get XAX II configuration files for on-board usb blaster II.

Where can I get that configuration image or logic source for EPM1270_M256FBGA?

What if I replace EPM1270 with EPM240 due to cost?
At that time, is the proper configuration file available?

Thank you in advance.

jo.
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Access onchip memory from NIOS II

February 19, 2018, 5:53 am
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Hi everyone,

I'm working on a project which includes a FPGA design with a NIOS II softcore. The NIOS II needs to interoperate with the FPGA logic through IO ports but I also want to exchange data with the FPGA logic. The easiest way would be if I had a possibility to directly access the onchip memory of the FPGA. Not only the part of the memory which is used by the NIOS II processor but the complete onchip memory. Is this possible and if yes what is the best way to do it?
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Array Declaration cases

February 19, 2018, 11:34 am
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Hi All,

Is there a difference in the following declarations:

case1:
reg [3:0][7:0] abc;
case2:
reg [3:0] abc [7:0];
case3:
reg abc [3:0][7:0];

What's the difference?

Thank you!
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Look Up Table of enum types -> declaration + usage -> how to?

February 19, 2018, 11:38 am
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Hi All,

I need to declare the following Look Up Table:

.......C2 .. C1 .. C0
L0....t0 ... t1 ... t2
L1....t2 ... t1 ... t0
L2....t1 ... t0 ... t2

where t0, t1 and t2 are enum elements of the LUT.

Each element of the LUT should be referenced by (L*,C*), which are also of enum type.

Ex:
LUT(C2,L0) should refer to t0
LUT(C1,L1) should refer to t1
LUT(C0,L2) should refer to t2

So, how should I define this LUT? How should I refer the elements in the LUT?

Thank you!
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Questions on PCIE communication protocol implementation in RIFFA

February 19, 2018, 11:02 pm
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I am using Riffa PCIE coding in Altera DE4


1) According to the completion TLP in http://xillybus.com/tutorials/pci-ex...torial-guide-1 , why https://github.com/KastnerRG/riffa/b...ctrl.v#L65-L68 allocated 12 bits and 8 bits for data and header respectively ?



2) For http://riffa.ucsd.edu/node/3 , why " Note that data on CHNL_RX_DATA may begin to arrive before CHNL_RX_ACK is pulsed, but the FIFO will never overflow. " ?

3) Why https://github.com/KastnerRG/riffa/b...32.v#L109-L124 and https://github.com/KastnerRG/riffa/b...32.v#L247-L286 using different number and types of FIFO ?
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Quartus 17 position of symbol labels different for VHDL and block diagram/schematic

February 20, 2018, 2:05 am
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When I create a symbol from a VHDL file, the labels are lined up with the pins properly. (center aligned)
But when I create a symbol from a block diagram/schematic file, the labels are below the pins.
The pins are aligned at the top of the text. This can become confusing when there are a lot of pins.
(see attached file)

Can this be changed, such that the block schematic symbol is similar to the vhdl symbol?
Attached Images
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Arria10 SoC, Angstrom Packge manager opkg issues!!

February 20, 2018, 2:49 am
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I'm running linux angstrom on Arria 10 SoC, i need to compile a program on the arm architecture but there is a lot of issues, to make it short here the error,

./configure: line 2176: pkg-config: command not found
./configure: line 2176: pkg-config: command not found
./configure: line 313: pr: command not found
./configure: line 313: pr: command not found
./configure: line 313: pr: command not found
./configure: line 313: pr: command not found
./configure: line 313: pr: command not found
./configure: line 313: pr: command not found
./configure: line 313: pr: command not found
./configure: line 313: pr: command not found
./configure: line 313: pr: command not found
./configure: line 313: pr: command not found
./configure: line 313: pr: command not found
./configure: line 313: pr: command not found
./configure: line 313: pr: command not found
./configure: line 313: pr: command not found
./configure: line 313: pr: command not found
./configure: line 313: pr: command not found
gcc is unable to create an executable file.
If gcc is a cross-compiler, use the --enable-cross-compile option.
Only do this if you know what cross compiling means.
C compiler test failed.
If you think configure made a mistake, make sure you are using the latest
version from Git. If the latest version fails, report the problem to the
ffmpeg-user@ffmpeg.org mailing list or IRC #ffmpeg on irc.freenode.net.
Include the log file "ffbuild/config.log" produced by configure as this will help
solve the problem.


i didn't understand if it's a gcc problem or not .
I need same help, thank you in advance if you have an idea and you need more information please tell me, thank you thank you
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help with TOP I/O management

February 17, 2018, 5:00 am
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Hello,

I am student who recently got my hands on DE10-nano. Up until now I was always working with Artix-7, Xilinx board. What I am trying to do is to migrate some of my projects to Intel-Quartus. What I am now fighting is an assignments of TOP IO. In Vivado(overall Xilinx products) I had constraints, where there was a IO assignments available, so-called master.xdc files. Here I will post what I am used to work with and I would like to ask someone, if could tell me how to get the same result here in Quartus.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.fixed_pkg.all;


entity TOP is
Port (


JA1 : out STD_LOGIC; -- pwm
btnL : in STD_LOGIC; --debouncerL for state_machine - reset
clk : in STD_LOGIC
);
end TOP;

With this I can take oscilloscope and see the PWM if I connect it to JA1 pin.

In quartus I can't find how to assign this output lets say to pin GPIO_0 D1, because I really don't know how to declare it.
Can anyone please tell me how does this work in quartus. I have never been working with it and I think I am stuck with the Vivado way of doing thing and can't comprehend how does it work here.

Thank you.
IK
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AVALON-MM Master Template on DE10 Lite

February 20, 2018, 8:52 am
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Hello, I am new to FPGA Development and in need of some help here.


I own a DE10 Lite and wish to build a system to read the contents of SDRAM. At first, all I want to do is read the contents of SDRAM. Later, I plan to update the RAM using the spi_slave_to_avalon_mm_master_bridge qsys component.


The problem I am facing in my code is that when data is read from memory, it appears to come back repeated. Let me explain,


I have an FPGA VHDL file/code that responds to a button press, the write process. When a button is pressed (called trigger), this process sequentially writes a counter to an incrementing memory addresses. The counter incrementally goes up with the address. The process stops at 19000. Memory address 0, should have a value of 1, memory address 2 should have a value of 2, etc.


Part of the system was setup in Platform Designer/Qsys. This part uses the SDRAM controlor, spi_slave_to_avalon_mm_master_bridge and the Avalon-MM Master Templates.


There is another process that also responsd to the trigger press, the read process. When the trigger is pressed, this process, sets up a delay of about 30000. So, when this process kicks off, all data should have already been written. This procesds, starts by looking at the contents of mem addrress 0 and issues a read, the read returns, memory address 1 is then read in then same way.


I note that this process reads values 1,1,2,2,3,3,4,4,5,5 when it should be reading values of 1,2,3,4,5 etc.


I'm pretty sure that the mem write porocess wrote sequentially in incrementing mem address correctly. I have beeen using signal tapp to see what is happening and suspect there is an error in the Avalon-MM Master Templates (Read), the write template is probably ok? not sure.


The SDRAM is 16 bits data. My process responds to the signals done, data_available, etc as I think it should with the proper timing, yet the data does not return properly. I am sure that the data is being written to the SDRAM correctly. If I change the write process to start at a number such as 30,


The read process reads 30,30 31,31 , 32 ,32 , etc


The problem seems to be somewhere in the read process.
Please advise how I can alleviate this. This is my first, and rather deep foray into FPGA dev and I want tobe successfull at this task of reading memory.




I have attached the project. I suspect, after trying a lot of variations, that the Avalon MM read template just doesn't wrok as advertised. I am looking ayt the documentation dated 09/08/2008. Note this was some template downloaded from Alter and added to platform designer.


Can someone look at this project and offer suggestions as to what to do? I would like to use the spi_slave_to_avalon_mm_master_bridge component and rely on the system intercoinnect fabric to arbitrate the readers and writers of SDRAM.
Thanks, Jeff
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