Export synthesized top-module and import in another project

February 20, 2018, 10:08 am

≫ Next: Altera Support / How to file a bug report about Quartus?

≪ Previous: AVALON-MM Master Template on DE10 Lite

I am working on a project where different engineers will be developing different modules of a large design completely separately. The design must be entirely bottom-up because the module developers may never know anything about the rest of the design. So, I need the ability to create a project, synthesize it, and export the netlist (along with a stub file). Then, in another project/design I need to import that netlist as a submodule.

I was able to do this easily in Quartus Standard (versions 12-17) by exporting a QXP netlist and importing that netlist in another project. In Quartus Pro 17.0, QXP netlists are no longer supported. I attempted to do the same thing using QDP files, but had no luck. I tried exporting the design as a "partition" but it will not let me export the top-module as a partition (only sub-modules). Export/import "design" does not help here either because when "importing", it seems to assume the design (QDB\) file being imported represents the entire design.

So, how can I export a synthesized design from the top-module and import the result (netlist or qdb...) in another project? As a reminder, my use-case involves lower-level designs that will never have any knowledge of the higher-level designs. So, it is not possible to create a full design and designate sub-modules as partitions.

Note: while I use the GUI to figure things out, ultimately my projects will be entirely command line, so any Tcl or command-line commands are very helpful (e.g. quartus_syn/quartus_cdb commands/options).

↧

Altera Support / How to file a bug report about Quartus?

February 20, 2018, 10:09 am

≫ Next: Cyclone V and data conversion board - arbitrary frequency

≪ Previous: Export synthesized top-module and import in another project

Hi All

I've been trying to file a couple of bug reports with Altera about Quartus Lite. These are fully repeatable, fully-documented, straightforward bug reports, one in the installer, one in qsys-generate. The particular issues have obvious workarounds but are nonetheless things you'd expect the developers to want to fix, and the fixes ought to be easy. The bugs wasted about two weeks of my time.

It's a month now and am getting frankly ridiculous responses from the Support Center for my service requests. Is there another channel to communicate with Altera on this kind of thing?

Altera makes lovely statements:

"We ensure that all products and services receive optimum attention to detail, from conception to delivery."

and

"DRIVE Quality in everything we do to ensure the Customers total quality experience!

Deliver defect-free products and services on time
Requirements are met at all times for internal and external customers
Improve continuously
Verify effectiveness
Every Intel employee is responsible"

https://www.altera.com/support/quali...y/quality.html

I'm not seeing it in practice. Any comments or suggestions from those more experienced with Altera? Any Altera staff here who can tell me the right channel to file bug reports?

Many thanks,
Jonathan.

↧

Cyclone V and data conversion board - arbitrary frequency

February 20, 2018, 10:34 am

≫ Next: Cyclone V and data conversion board - arbitrary frequency

≪ Previous: Altera Support / How to file a bug report about Quartus?

Hello Altera Forums,

I'm using a Cyclone V GX Starter Kit with a data conversion board plugged into the HSMC slot.

I am using a 50MHz clock generated by a PLL. This clock is sent to pins 95 and 155 of the HSMC (for ADC channels A and B ). On the DCB card, I have pins 1 and 3 connected on J3 and J7, as per the manual.

I am able to record data with this with no issues (Signaltap_50MHz.png):

When I change to PLL clock to some other frequency however, the data I get is nonsense (example is at 40MHz, but the same issue occurs at other frequencies. I've tried 60, 100, and 150MHz) (Signaltap_40MHz.png):

Is there anything I should be checking to make this work properly? I have read the manual for the DCB, and found no indication that it can't run at an arbitrary frequency.

If there's any more info I can send to help solve this, please let me know.

Thank you for your assistance,
-Sam

Attached Images

Signaltap_50MHz.jpg (19.3 KB)
Signaltap_40MHz.jpg (20.5 KB)

↧

Cyclone V and data conversion board - arbitrary frequency

February 20, 2018, 10:45 am

≫ Next: Issues with PLL's in Cyclone V SoC

≪ Previous: Cyclone V and data conversion board - arbitrary frequency

Hello Altera Forums,

I'm using a Cyclone V GX Starter Kit with a data conversion board plugged into the HSMC slot.

I am using a 50MHz clock, generated by a PLL and sent to pins 95 and 155 of the HSMC (for channels A and B ).
On the DCB card, I have pins 1 and 3 connected on J3 and J7, as per the manual.

With this setup, I can take data with no problems. (see Signaltap_50MHz.png)

If I change the PLL clock to an arbitrary frequency, the data I get makes no sense. (see Signaltap_40MHz.png)
I have tried 60, 100, and 150MHz, and encountered the same problems.

Note that in the attached files, the clock for signaltap is the PLL clock which should be sent to the DCB as well.

My suspicion is that the DCB board is not using the clock I'm sending and is simply using a 50MHz clock, so when I use a 50MHz PLL clock, it lines up with the DCB clock and appears to be working.

Is there anything obvious that I should be trying?

If there's more information that could help solve the problem, let me know.

Thanks in advance,
-Sam

Attached Images

Signaltap_50MHz.jpg (19.3 KB)
Signaltap_40MHz.jpg (20.5 KB)

↧

Issues with PLL's in Cyclone V SoC

February 20, 2018, 12:36 pm

≫ Next: calculate power consumption constantly

≪ Previous: Cyclone V and data conversion board - arbitrary frequency

Hello,

Does anyone have guidelines as to how the fPLL's inputs and outputs are to be connected to the logic?

I have been unable to get hold of a proper method for a very long time.

Board: Arrow SoCkit Evaluation board.
Cyclone V
5CSXFC6D631C6

Here is a sample top level file:

module top(
input clk,
input rst,
input driver_clk,
output pll_out,
output locked_port,
output data
);

driver d1(
.clk(driver_clk),
.rst(rst),
.data_out(data)
);

pll pll_inst (
.refclk (clk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (pll_out), // outclk0.clk
.locked (locked_port) // locked.export
);
endmodule

If someone could provide the pin numbers for the clk, driver_clk and pll_out, it would be much helpful

Thanks for your time.

↧

calculate power consumption constantly

February 20, 2018, 1:15 pm

≫ Next: Clock to 1Ghz with Altera PLL ?

≪ Previous: Issues with PLL's in Cyclone V SoC

Hi,

I've got a nallatech p385a and I want to see how much power is being consumed during execution. So far the only available tool is "aocl diagnose", but if I run it when the opencl code is running, then the OpenCL host code will stop responding. And when I kill the host code, the whole system crashes.

Now, how can I measure power consumption?

↧

Clock to 1Ghz with Altera PLL ?

February 20, 2018, 1:36 pm

≫ Next: No JTAG after AS programming on EP2C5T144

≪ Previous: calculate power consumption constantly

Hello,

I have a DE0-Nano-SoC with Cyclone V 5CSEMA4U23C6N and a external-clock to 50Mhz. I would like a clock to 1Ghz with Altera PLL, is it possible ?
Today, I have a clock to 800Mhz with PLL Altera but I can't exceed 800Mhz !

Thank you very much.

PS : Sorry for my English, I am French.

↧

No JTAG after AS programming on EP2C5T144

February 20, 2018, 2:56 pm

≫ Next: Arria 10 EPCQL Controller

≪ Previous: Clock to 1Ghz with Altera PLL ?

I tried just a hello world example on EP2C5T144 on a simple dev board. Programming via JTAG worked. I switched to AS and programmed it - all worked.

However, when I switch back to JTAG now, it doesn't work. When debugging JTAG, it says Incorrect clock and TDI value. AS programming still works.

Did I miss something obvious?

↧

Arria 10 EPCQL Controller

February 20, 2018, 4:04 pm

≫ Next: Arria 10 SoC Development Kit FPGA Memory Interface

≪ Previous: No JTAG after AS programming on EP2C5T144

Hi,

I am trying to program my EPCQ-512L from the HPS running Linux. I have the Altera Serial Flash Controller connected from its avl_csr and avl_mem connected to the HPS using the hps2fpga lightweight bridge. I have tried to write the EPCQ and have been successful in writing zeroes. From what I have gathered, I need to erase the sector, then write my values because it erasing sets all the values in the sector to '1'. Here lies my problem; following https://www.altera.com/en_US/pdfs/li...mbedded_ip.pdf , starting on page 153 about the Altera Serial Flash Controller I tried to write to the FLASH_MEM_OP register to erase sectors. I tried writing 0x2 to the register to erase the sector data, but nothing seems to change. I have tried writing other values and from what I can see (when reading the values back from the epcq) there is never a change. I also tried reading the status register to see if there are processes occurring, but it always reads 0.
Also when I try to read either the FLASH_RD_SID, FLASH_RD_RDID, FLASH_ISR, or FLASH_IMR, the HPS seems to stop responding and I need to reload my .sof. I use either ssh terminal or serial terminal to communicate with my system and when I try to read any of the mentioned registers, the system stops responding on both ssh and serial. I have other signals connected to the lightweight bridge and I have not run into this symptom before. I think this could be part of the problem; maybe the control register is not working at all, but I am not sure where to start debugging this. Any help or points in a direction would be much appreciated.

Thank you in advance :)

↧

Arria 10 SoC Development Kit FPGA Memory Interface

February 20, 2018, 6:51 pm

≫ Next: EPCQ and EPCQ-L are discontinued (notification 02/14/2018)

≪ Previous: Arria 10 EPCQL Controller

I am using Arria 10 SoC Development Kit right now and trying to get access to the FPGA memory.

What I have done is generating the EMIF IP with preset ( Arria 10 SoC Development Kit FPGA Memory 72x) together with the Avalon bus DDR test verilog code.
But still cannot read from DDR4. Here I posted the captured waveform from signaltap. Is there anyone could help?
The name of each signal is quite obvious

Attached Images

rrrrr.jpg (20.4 KB)

↧

EPCQ and EPCQ-L are discontinued (notification 02/14/2018)

February 21, 2018, 12:52 am

≫ Next: RGMII MODE ethernet loop back program for cyclone 5 GT evaluation board

≪ Previous: Arria 10 SoC Development Kit FPGA Memory Interface

Hi,

I just found this "PRODUCT DISCONTINUANCE NOTIFICATION PDN1802" which says that EPCQL256-512-1024 and some EPCQ are discontinued because flash vendor is stopping production.
https://media.digikey.com/pdf/PCNs/Altera/PDN1802.pdf

Is there official alternatives for EPCQ-L recommended for new designs? Now it's written everywhere that Altera can not guarantee any replacement part behavior.
I already use in the past Spansion or Micron replacement parts. But now, common packages are BGA24 or WSON and both are not easy to solder/desolder manually to test parts.

So as conf flash are critical parts of FPGA designs, we should get soon some official guidelines or white paper. Or maybe new flash part?
Do anybody found something?

Thanks for feedbacks.

↧

RGMII MODE ethernet loop back program for cyclone 5 GT evaluation board

February 21, 2018, 2:40 am

≫ Next: Compute units on emulator

≪ Previous: EPCQ and EPCQ-L are discontinued (notification 02/14/2018)

Hi

I have cyclone 5 gt evaluation board.
I want to check loop back test from board to my PC.
I added triple speed Ethernet ip core in quartux-2 but it is not working,i attached my verilog code.
can anyone have reference program for simple Ethernet loop-back test by quartux2 ?

Thanks
DEEPAK KUMAR

Attached Files

verilog_code.txt (3.2 KB)

↧

Compute units on emulator

February 21, 2018, 2:48 am

≫ Next: DE10-Nano OpenCL examples compilation with Quartus Prime and OpenCL SDK 17.1

≪ Previous: RGMII MODE ethernet loop back program for cyclone 5 GT evaluation board

Hi,
I would like to say if the emulator considers the use of multiple compute units. I do not have a physical board for working, so if I had more than one compute unit, how does the emulator work? Thanks for your help

↧

DE10-Nano OpenCL examples compilation with Quartus Prime and OpenCL SDK 17.1

February 21, 2018, 1:48 am

≫ Next: design simulation

≪ Previous: Compute units on emulator

Hello.

During "boardtest" example compilation from DE10_Nano_OpenCL.pdf with Quartus Prime and OpenCL SDK 17.1 I have the next exceptions:

Code:

E:\intelFPGA\17.1\hld\board\terasic\de10_nano\examples\boardtest>aoc device/boardtest.cl -o bin/boardtest.aocx --board de10_nano_sharedonly --reportWarning: Please use -board=<value> instead of --board <value>

Warning: Please use -report instead of --report

aoc: Selected target board de10_nano_sharedonly

aoc: Running OpenCL parser....

e:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/device/boardtest.cl:77:20: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance

    __global uint *dst,

                   ^

e:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/device/boardtest.cl:78:26: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance

    __global const uint *index,

                         ^

2 warnings generated.

aoc: Optimizing and doing static analysis of code...





!===========================================================================

! The report below may be inaccurate. A more comprehensive

! resource usage report can be found at boardtest/reports/report.html

!===========================================================================





+--------------------------------------------------------------------+

; Estimated Resource Usage Summary                                   ;

+----------------------------------------+---------------------------+

; Resource                               + Usage                     ;

+----------------------------------------+---------------------------+

; Logic utilization                      ;   38%                     ;

; ALUTs                                  ;   22%                     ;

; Dedicated logic registers              ;   18%                     ;

; Memory blocks                          ;   32%                     ;

; DSP blocks                             ;    0%                     ;

+----------------------------------------+---------------------------;

Compiling for FPGA. This process may take a long time, please be patient.

Error (10759): Verilog HDL error at boardtest_system.v(615): object kernel_receiver_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 615

Error (10112): Ignored design unit "kernel_receiver_partition_wrapper" at boardtest_system.v(589) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 589

Error (10759): Verilog HDL error at boardtest_system.v(844): object kernel_sender_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 844

Error (10112): Ignored design unit "kernel_sender_partition_wrapper" at boardtest_system.v(817) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 817

Error (10759): Verilog HDL error at boardtest_system.v(1096): object mem_read_writestream_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1096

Error (10112): Ignored design unit "mem_read_writestream_partition_wrapper" at boardtest_system.v(1050) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1050

Error (10759): Verilog HDL error at boardtest_system.v(1367): object mem_readstream_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1367

Error (10112): Ignored design unit "mem_readstream_partition_wrapper" at boardtest_system.v(1321) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1321

Error (10759): Verilog HDL error at boardtest_system.v(1626): object mem_writestream_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1626

Error (10112): Ignored design unit "mem_writestream_partition_wrapper" at boardtest_system.v(1592) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1592

Error (10759): Verilog HDL error at boardtest_system.v(1861): object nop_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1861

Error (10112): Ignored design unit "nop_partition_wrapper" at boardtest_system.v(1839) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1839

Error (10759): Verilog HDL error at boardtest_system.v(2116): object reorder_const_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2116

Error (10112): Ignored design unit "reorder_const_partition_wrapper" at boardtest_system.v(2059) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2059

Error (10112): Ignored design unit "kernel_receiver_top_wrapper_0" at boardtest_system.v(2352) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2352

Error (10112): Ignored design unit "kernel_sender_top_wrapper_0" at boardtest_system.v(2427) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2427

Error (10112): Ignored design unit "mem_read_writestream_top_wrapper_0" at boardtest_system.v(2506) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2506

Error (10112): Ignored design unit "mem_readstream_top_wrapper_0" at boardtest_system.v(2623) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2623

Error (10112): Ignored design unit "mem_writestream_top_wrapper_0" at boardtest_system.v(2740) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2740

Error: Quartus Prime Analysis & Synthesis was unsuccessful. 19 errors, 2 warnings

Error (293001): Quartus Prime Full Compilation was unsuccessful. 21 errors, 2 warnings

Error: Flow compile (for project E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/top) was not successful

Error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.

Error (23031): Evaluation of Tcl script e:/intelfpga/17.1/quartus/common/tcl/internal/qsh_flow.tcl unsuccessful

Error: Quartus Prime Shell was unsuccessful. 28 errors, 2 warnings

Error: Compiler Error, not able to generate hardware

How I can fix this exception or how I can receive free test license for OpenCl v.16.1 for testing?
Link to DE10-Nano resources, BSP(Board Support Package) for Intel FPGA SDK OpenCL 16.1: http://www.terasic.com.tw/cgi-bin/pa...=1046&PartNo=4

Thanks.

↧

design simulation

February 21, 2018, 7:32 am

≫ Next: FPP Configuration, Bank 2A and reuse

≪ Previous: DE10-Nano OpenCL examples compilation with Quartus Prime and OpenCL SDK 17.1

hello

i've done a design using quartus 17.1 pro. but i coudn't simulate this design. i tried to convert it to a VHDL script but i dindn't know how

how can i simulate it or convert it

↧

FPP Configuration, Bank 2A and reuse

February 21, 2018, 7:43 am

≫ Next: [Reprograming] FPGA Handle CODE

≪ Previous: design simulation

In a new C10GX / Arria10 design we are employing 16-bit FPP Configuration of the FPGA via a Host processor:

i) Before FPGA configuration, the (same) 16-bit bus is to be used to boot the Host from a parallel Flash part also residing on the bus (the FPGA is inactive at this time).

ii) During FPGA configuration, the (same) 16-bit bus is used to configure the FPGA via the Host (the parallel Flash part is inactive at this time).

iii) After FPGA configuration, the (same) 16-bit bus is used as the run-time interface between the Host and the FPGA (the parallel Flash part is normally inactive at this time).

We have some questions:

1) Does Section 5.7.8 of C10GX51003 2017.11.10 (Guideline: Usage of I/O Bank 2A for External Memory Interfaces) apply to this case when it states:
"Do not use I/O bank 2A's pins that are required for configuration-related operations as external memory interface pins, even after configuration is complete. For example:
Pins that are used for the Fast Passive Parallel (FPP) configuration bus"

Runtime reuse of the FPP configuration bus seems logical given the size of the 16-bit bus that is already dedicated between the Host and the FPGA for the FPP configuration function. In fact, the Host only has one parallel bus for this purpose. Why would the above document caution against this (re)use of the configuration bus? Or does "External Memory Interfaces" perhaps apply only to IP Core implementations?

2) For Case i) above, are we correct in deducing that a powered FPGA will not load the configuration pins if we drive nCE high (and pull nConfig low), or is there a better mechanism not involving an external bus buffer? This is similar to the Note in Section 7.2.1.5.1 in C10GX51003 2017.11.10.

3) For Case ii) above, we would drive nCE low via a GPIO from the Host before releasing nConfig.

4) For Case iii) above, this thread indicates that we could continue to drive DCLK: http://www.alteraforum.com/forum/showthread.php?t=57313. DCLK will be reused as nWE on another FPGA pin (connected in parallel) for this Case.
Could / should we also again drive nCE high in this state?

5) Is the use of nCE described above valid and feasible in order to enable the intended functionality?

↧

[Reprograming] FPGA Handle CODE

February 21, 2018, 8:41 am

≫ Next: How to use SCLR port of an Flip flop in Verilog?

≪ Previous: FPP Configuration, Bank 2A and reuse

Hi people!

After i before one kernel for executing it appears me the following code:
Reprogramming device [0] with handle 1

Then, after the first kernel is finished, i submit another kernel and get the following code:
Reprogramming device [0] with handle 33

What are the messages corresponding to this codes?

↧

How to use SCLR port of an Flip flop in Verilog?

February 21, 2018, 9:57 am

≫ Next: Can I use MAX3000 in Quartus lite 17.1

≪ Previous: [Reprograming] FPGA Handle CODE

I am using Quartus Prime 17.1 and I am trying to use SCLR port of the flip flop to synchronously reset the flip flop, however it synthesize a mux driven by reset input. My code is:

Code:

module ff(clk, q,a,b, reset,ce,asynch_load,data,synch_reset,synch_load);



    input logic clk,a,b,reset,ce,asynch_load,data,synch_reset,synch_load;

    logic d;

    

    output logic q;

    

    assign d = ((((q&a)|b)));



    always @ (negedge reset or posedge asynch_load or posedge clk)

    begin

        // The asynchronous reset signal has highest priority

        if (!reset)

        begin

            q <= 1'b0;

        end

        // Asynchronous load has next priority

        else if (asynch_load)

        begin

            q <= data;

        end

        else

        begin

            // At a clock edge, if asynchronous signals have not taken priority,

            // respond to the appropriate synchronous signal.

            // Check for synchronous reset, then synchronous load.

            // If none of these takes precedence, update the register output 

            // to be the register input.

            if (ce)

            begin

                if (synch_reset)

                begin

                    q <= 1'b0;

                end

                else if (synch_load)

                begin

                    q <= data;

                end

                else

                begin

                    q <= d;

                end

            end

        end

    end

    

endmodule

And here is the RTL of synthesized architecture:

How could I use SCLR input to reset the flip flop value?

Attached Images

Screenshot (3).jpg (18.8 KB)

↧

Can I use MAX3000 in Quartus lite 17.1

February 21, 2018, 9:59 am

≫ Next: Unconstrained paths in timequest result in setup violation

≪ Previous: How to use SCLR port of an Flip flop in Verilog?

Dear reader,
Does any one know if I can use/install the MAX3000 CPLD family (EPM3064) in Quartus 17.1. It was available in version 13 but has disappeared.
If this is not possible what is the best I can do install version 13 instead of 17? Some advice what is best to do would help.
Hope that some can help me out.
Regards Oscar Goos

↧

Unconstrained paths in timequest result in setup violation

February 21, 2018, 10:46 am

≫ Next: Is it possible to change jtag id?

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Hi,
I have a code which I am using in Qsys. The ports are reported in unconstrained paths in Timequest. What is the best way to eliminate them?
I have a clean timing before constraining these ports(input/output).

When I try to set input or output delay, then I get a setup violation of around -6.

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