how to send a 48 bit command to an sd card using spi ip which has 32 bit wide tx and rx data registers? sd card is formatted in fat 16-2 gb and fat32-4gb......
↧
Using SPI IP with Nios.
↧
Detect JTAG programming with ALT_REMOTE_UPDATE ip
Hi,
my Cyclone IV design uses ALT_REMOTE_UPDATE ip to switch between a factory and application
bitstream. This works fine.
Now I want to skip any rebooting when the FPGA is currently programmed via JTAG.
The Altera Remote Update IP Core User Guidee states that bit 4 of RU_RECONFIG_TRIGGER_CONDITION
is set on external configuration (nCONFIG assertion). Does this mean it should be set when programming via
JTAG also?
Is there any other way to detect if the current image is loaded via JTAG?
Regards,
Matthias
my Cyclone IV design uses ALT_REMOTE_UPDATE ip to switch between a factory and application
bitstream. This works fine.
Now I want to skip any rebooting when the FPGA is currently programmed via JTAG.
The Altera Remote Update IP Core User Guidee states that bit 4 of RU_RECONFIG_TRIGGER_CONDITION
is set on external configuration (nCONFIG assertion). Does this mean it should be set when programming via
JTAG also?
Is there any other way to detect if the current image is loaded via JTAG?
Regards,
Matthias
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↧
Begining FPGA,give me a good way to learn FPGA
Hi guys,I am learning FPGA perfectly,where can I start from in order to?
I am using Verilog, but my informations are so messy.
I am using Verilog, but my informations are so messy.
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MAX10 remote system upgrade
Hi,
I am currently implementing the remote system upgrade for the MAX10/04 but have a few issues. I've been googling but haven't found any related information. Hopefully those of you have experience with this MAX10 configuration can throw some lights for me:-P
1. there are a few options of the configuration mode including dual/single image, or compressed/uncompressed image, we configured these when generating the altera_onchip_flash core. However after building the quartus project, is there any way that we can read these configuration from the flash , ie, the header of the RPD file?
2. when use the compressed image mode, as stated in the MAX10 datasheet, a minimum of 30% compression ration is required. My compression ration is around 50~60% with 65% resource usage, which is not a matter as now. However I'm a bit concern about this compression ratio as when the design grows the device can be rather full (ie 99% full), if that happens will the compression ratio achieve 70%?
3. the timing issue. the only guaranteed present clock resource is the on chip oscillator whose frequency ranges from 55 to 116 MHz, this clock will also be the clock input to the altera_onchip_flash. In the IP configuration dialogue, I used 116MHz as the frequency input so this is hitting the timing limit. However I found the timing constraint constantly failed if I put a little bit more logics around the flash, even a change of version number from 1 to 2!!! I didn't see other people have similar issue, so wondering whether I did it correctly, any thought? The failed path is in the data path from one register to another which is quite far away from each other in the placement view. Can we place any restriction to get around with it?
Thanks in advance,
Zifang
I am currently implementing the remote system upgrade for the MAX10/04 but have a few issues. I've been googling but haven't found any related information. Hopefully those of you have experience with this MAX10 configuration can throw some lights for me:-P
1. there are a few options of the configuration mode including dual/single image, or compressed/uncompressed image, we configured these when generating the altera_onchip_flash core. However after building the quartus project, is there any way that we can read these configuration from the flash , ie, the header of the RPD file?
2. when use the compressed image mode, as stated in the MAX10 datasheet, a minimum of 30% compression ration is required. My compression ration is around 50~60% with 65% resource usage, which is not a matter as now. However I'm a bit concern about this compression ratio as when the design grows the device can be rather full (ie 99% full), if that happens will the compression ratio achieve 70%?
3. the timing issue. the only guaranteed present clock resource is the on chip oscillator whose frequency ranges from 55 to 116 MHz, this clock will also be the clock input to the altera_onchip_flash. In the IP configuration dialogue, I used 116MHz as the frequency input so this is hitting the timing limit. However I found the timing constraint constantly failed if I put a little bit more logics around the flash, even a change of version number from 1 to 2!!! I didn't see other people have similar issue, so wondering whether I did it correctly, any thought? The failed path is in the data path from one register to another which is quite far away from each other in the placement view. Can we place any restriction to get around with it?
Thanks in advance,
Zifang
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[ModelSim] how to run a bash script from within ModelSim?
Hi All,
I'd like to run a bash script from within ModelSim Transcript window. How can I do so?
Thank you!
I'd like to run a bash script from within ModelSim Transcript window. How can I do so?
Thank you!
↧
↧
Is it possible to implement async ROM/RAM in Stratix family?
Hi,
I need to have an asynchronous RAM/ROM in Cyclone IV E for my MIPS processor. Unfortunately, Stratix device family does not support LPM_ROM or LPM_RAM_DQ without providing the inclock/outclock of the units. Any way to go around this limitation?
Currently, I have made a custom ROM/RAM with ARRAY and STD_LOGIC_VECTOR but I don't know how to initialize them outside of
I need to have an asynchronous RAM/ROM in Cyclone IV E for my MIPS processor. Unfortunately, Stratix device family does not support LPM_ROM or LPM_RAM_DQ without providing the inclock/outclock of the units. Any way to go around this limitation?
Currently, I have made a custom ROM/RAM with ARRAY and STD_LOGIC_VECTOR but I don't know how to initialize them outside of
Code:
(OTHERS (OTHERS => '0'))↧
Advice and examples for Interlaken protocol
Dear all,
I would like some clarifications about Interlaken implementation on Altera/Intel FPGA.
I need to implement a single lane communication between two FPGAs on StratixV/ArriaV-GZ at 10-12.5 Gbps and I need a backpressure/flow control system.
Is there any better choice than Interlaken? in my case I am force to use v1, because v2 has min 4 lanes.
Reading the documentation I understand that the PHY is controlled and monitor through Avalon-MM, but Interlaken IP v1 is not available anymore on Platform Designer/Qsys.
Is there any way to use the old Interlaken IP created by Quartus inside a qsys project?
I have already tried the basic examples, but without luck. Some are without an Avalon interface, so they cannot be monitored easily by the Transceiveir toolkit. I believed that an avalon interface was mandatory. Instead I found one example w/o that .
Do you have any additional example that I can try to resue/adapt?
Many thanks for your time,
Riccardo
I would like some clarifications about Interlaken implementation on Altera/Intel FPGA.
I need to implement a single lane communication between two FPGAs on StratixV/ArriaV-GZ at 10-12.5 Gbps and I need a backpressure/flow control system.
Is there any better choice than Interlaken? in my case I am force to use v1, because v2 has min 4 lanes.
Reading the documentation I understand that the PHY is controlled and monitor through Avalon-MM, but Interlaken IP v1 is not available anymore on Platform Designer/Qsys.
Is there any way to use the old Interlaken IP created by Quartus inside a qsys project?
I have already tried the basic examples, but without luck. Some are without an Avalon interface, so they cannot be monitored easily by the Transceiveir toolkit. I believed that an avalon interface was mandatory. Instead I found one example w/o that .
Do you have any additional example that I can try to resue/adapt?
Many thanks for your time,
Riccardo
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MAX 10: a clock for SPI
Is using an external clock without a clock buffer causing any problem?
I'm implementing SPI slave.
An external SPI clock is directly from a pin(not a clock pin, but just an IOpin) of the FPGA(10M08SAE144C8G).
Should I use a clock buffer for this?
The reason why I have this question is I got some timing violations.
Here are my simple codes.
-----------------------------------------------------------------
always @(negedge sclk or posedge in_CSn)
if (in_CSn) Cnt <= 3'd7;
else if (Cnt == 3'd0) Cnt <= 3'd0;
else Cnt <= Cnt - 1'b1;
assign out_MISO = (~in_CSn)? pData[Cnt] : 1'b0;
-----------------------------------------------------------------
And the timing violations are from "Cnt". These are very simple logics,
But I cannot understand why this causes timing violations.
Timing report shows this clock's restricted fMax is 250Mhz.
I'm implementing SPI slave.
An external SPI clock is directly from a pin(not a clock pin, but just an IOpin) of the FPGA(10M08SAE144C8G).
Should I use a clock buffer for this?
The reason why I have this question is I got some timing violations.
Here are my simple codes.
-----------------------------------------------------------------
always @(negedge sclk or posedge in_CSn)
if (in_CSn) Cnt <= 3'd7;
else if (Cnt == 3'd0) Cnt <= 3'd0;
else Cnt <= Cnt - 1'b1;
assign out_MISO = (~in_CSn)? pData[Cnt] : 1'b0;
-----------------------------------------------------------------
And the timing violations are from "Cnt". These are very simple logics,
But I cannot understand why this causes timing violations.
Timing report shows this clock's restricted fMax is 250Mhz.
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"Report path" in time Quest timing analyzer, optimization of orignal circuit
I want to see paths in my original circuit along with logic element within paths.
i write a verilog code, compile it, and then run the time quest timing analyzer
in order to check paths and logic element within paths.
but timing analyzer optimizes the orignal circuit and generate report paths according to it.
e-g in verilog and and RTL view, i have 3 flipflops and 10 gates and time quest optimizes soo much that
in post mapping / post fitting i got 3 FlipFlops and 2 gates. and "Report path" show path according to
optimize circuit.
Is there any way to get "report path" before optimization or without optimization,
so that i can get paths in my original circuit.
Immediate help in this regard will be appreciated
Thankyou for your time and consideration
i write a verilog code, compile it, and then run the time quest timing analyzer
in order to check paths and logic element within paths.
but timing analyzer optimizes the orignal circuit and generate report paths according to it.
e-g in verilog and and RTL view, i have 3 flipflops and 10 gates and time quest optimizes soo much that
in post mapping / post fitting i got 3 FlipFlops and 2 gates. and "Report path" show path according to
optimize circuit.
Is there any way to get "report path" before optimization or without optimization,
so that i can get paths in my original circuit.
Immediate help in this regard will be appreciated
Thankyou for your time and consideration
↧
↧
Error: interrupt is not connected for JTAG in Nios II
I am new babie to Altera Quartus. To get familiar with the tool, initially i have started to execute "Hello World" in NIOS II through Youtube tutorial. But I am getting this error when building a Nios II project.
alt_sys_init.c:(.text+0x8): warning: Error: Interrupt not connected for JTAG_UART. You have selected the interrupt driven version of the ALTERA Avalon JTAG UART driver, but the interrupt is not connected for this device. You can select a polled mode driver by checking the 'small driver' option in the HAL configuration window, or by using the -DALTERA_AVALON_JTAG_UART_SMALL preprocessor flag.
Please help me to fix it. I am using Quartus II 14.1 (64-bit) Web edition.
alt_sys_init.c:(.text+0x8): warning: Error: Interrupt not connected for JTAG_UART. You have selected the interrupt driven version of the ALTERA Avalon JTAG UART driver, but the interrupt is not connected for this device. You can select a polled mode driver by checking the 'small driver' option in the HAL configuration window, or by using the -DALTERA_AVALON_JTAG_UART_SMALL preprocessor flag.
Please help me to fix it. I am using Quartus II 14.1 (64-bit) Web edition.
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Unable to execute Hello World in Quartus Web edition
Hello Friends,
I am struggling to execute "Hello world" :confused: :cry:.
Once i programmed my .sof file to the QuartusII programmer , and the following message pops up that chain.cdf is modified, Do you want changes to be saved.
Then second issue: ".elf" file is unable to detect or add. .ELF file is missing in NIOS.
Please help me
I am struggling to execute "Hello world" :confused: :cry:.
Once i programmed my .sof file to the QuartusII programmer , and the following message pops up that chain.cdf is modified, Do you want changes to be saved.
Then second issue: ".elf" file is unable to detect or add. .ELF file is missing in NIOS.
Please help me
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Timing constraints for 2 clocks, phase shifted by 90 degrees
Hello all,
I have a design, in which two clocks are used. One main clock and another one with 90 degree fixed phase shift. There are registers that are related to these clocks, for example regA clocked by main_clk is connected to the regB clocked by clk90.
How can I set the correct timing constraints in this case? Is there any available literature for this subject?
Thanks in advance.
I have a design, in which two clocks are used. One main clock and another one with 90 degree fixed phase shift. There are registers that are related to these clocks, for example regA clocked by main_clk is connected to the regB clocked by clk90.
How can I set the correct timing constraints in this case? Is there any available literature for this subject?
Thanks in advance.
↧
Issues on PCI Transfers and Kernels Execution Overlapping.
Hi everybody,
We have a piece of software that uses a double buffering pipeline to overlap FPGA execution, PCI transfers, and CPU-side competition.
The software is pretty throughput intensive, and at each cycle of the pipeline we do many PCI transfers, execute many many kernels on the FPGA.
Obviously, the best would be to be able to keep the PCI bus and the FPGA as busy as possible. However, we know that our FPGA is equipped with only one DMA engine; thus, transfers from and to the FPGA are going to be serialized, but we can live with that.
However, we see few issues:
1. Sometimes, when a PCI transfer is in-flight, no kernel execution is scheduled on the FPGA until the PCI transfer is concluded. Note that the two tasks are independent and the completion of one should not stall the execution other. (See the red rectangles in the attached first.png file.)
2. The vice-versa of the previous point also happens. Which is, no PCI transfers is executed until the current kernels on the FPGA concluded. (See the orange rectangle in the attached first.png file.)
3. [The major problem] We saw that after few hundreds of cycles (thousands of kernels and PCI transfers), time gaps from one task and another start to appear. Gaps that get worst and worst with the time and that become unacceptable at some time. Making a cycle lasts around 30 seconds instead than the usual 3.5/4 seconds. It's true that the software runs for around one hour performing hundreds of thousands of PCI transfers and kernel executions, but we believe this should not happen. And it does not occur when using a GPU.
We have no idea whether this is a problem of the driver or of the FPGA itself but we are thinking to something like "the driver keeps a list of events/object, and it has to traverse all the list every time making it slower and slower the more task you do." (See the purple rectangle in the attached second.png file.)
We would like to know if some of you experienced similar problems.
Also, any idea, comment, and suggestion are welcome!
OS: Centos 7.4
FPGA board: Nallatech 510T
Software environment: IntelFPGA SDK v17.1 build 270 and BSP R001.005.0004
We have a piece of software that uses a double buffering pipeline to overlap FPGA execution, PCI transfers, and CPU-side competition.
The software is pretty throughput intensive, and at each cycle of the pipeline we do many PCI transfers, execute many many kernels on the FPGA.
Obviously, the best would be to be able to keep the PCI bus and the FPGA as busy as possible. However, we know that our FPGA is equipped with only one DMA engine; thus, transfers from and to the FPGA are going to be serialized, but we can live with that.
However, we see few issues:
1. Sometimes, when a PCI transfer is in-flight, no kernel execution is scheduled on the FPGA until the PCI transfer is concluded. Note that the two tasks are independent and the completion of one should not stall the execution other. (See the red rectangles in the attached first.png file.)
2. The vice-versa of the previous point also happens. Which is, no PCI transfers is executed until the current kernels on the FPGA concluded. (See the orange rectangle in the attached first.png file.)
3. [The major problem] We saw that after few hundreds of cycles (thousands of kernels and PCI transfers), time gaps from one task and another start to appear. Gaps that get worst and worst with the time and that become unacceptable at some time. Making a cycle lasts around 30 seconds instead than the usual 3.5/4 seconds. It's true that the software runs for around one hour performing hundreds of thousands of PCI transfers and kernel executions, but we believe this should not happen. And it does not occur when using a GPU.
We have no idea whether this is a problem of the driver or of the FPGA itself but we are thinking to something like "the driver keeps a list of events/object, and it has to traverse all the list every time making it slower and slower the more task you do." (See the purple rectangle in the attached second.png file.)
We would like to know if some of you experienced similar problems.
Also, any idea, comment, and suggestion are welcome!
OS: Centos 7.4
FPGA board: Nallatech 510T
Software environment: IntelFPGA SDK v17.1 build 270 and BSP R001.005.0004
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VHDL code works when compiled on Quartus Prime V15.1 but breaks on V17.1
Hello,<br>
I have code working on a hardware design that was compiled using Quartus Prime version 15.1. I installed QP version 17.1 and compiled the same code but the code did not work as expected. I have an IO port that was not being used (pins were assigned in top level entity) and added code (highlighted in red below) and recompiled in 17.1 and it seems to have "fixed" the code (very strange). I added the IO port to help debug the problem.<br>
<br>
I am not sure if it is an issue with the code or a compiler issue. Both compiler versions were used with default settings.<br>
<br>
Any help with understanding the compiler settings would be appreciated. (some code was deleted to fit here)<br>
<br>
entity mip_device is<br>
port<br>
(<br>
RESETn : in std_logic;<br>
CLK : in std_logic; -- Local Bus Clock<br>
ENABLE : inout std_logic; -- NOT(STATUS(15))<br>
<br>
<br>
-- Inputs from the Top Level Entity:<br>
MIP_CLK : in std_logic;<br>
<br>
<br>
-- Outputs to the MIP Bus (we can read them too):<br>
STATUS : inout std_logic_vector(15 downto 0);<br>
MBX_W1 : inout std_logic_vector(15 downto 0);<br>
MBX_W2 : inout std_logic_vector(15 downto 0);<br>
MBX_W3 : inout std_logic_vector(15 downto 0);<br>
MBX_W4 : inout std_logic_vector(15 downto 0);<br>
<br>
<br>
-- Inputs from the MIP Bus:<br>
CTRL : in std_logic_vector(15 downto 0);<br>
MIP_RADDR : in std_logic;<br>
MIP_WADDR : in std_logic;<br>
BUF_OVERRUN : in std_logic;<br>
BUF_RDY : in std_logic;<br>
BUF : in mip_buf_t;<br>
<br>
-- Inputs from the Local Bus:<br>
LCS : in std_logic; -- Local Bus Chip Select<br>
LALE : in std_logic; -- Local Bus Address Latch Enable<br>
LOE : in std_logic; -- Local Bus Output Enable<br>
LWE : in std_logic; -- Local Bus Write Enable<br>
LADDR : in std_logic_vector(7 downto 0);<br>
<br>
-- Outputs:<br>
IRQn : inout std_logic;<br>
IO : inout std_logic_vector(15 downto 0);<br>
IRQ_OE : out std_logic;<br>
<font color="#ff0000"><strong>ioout : out std_logic_vector(7 downto 0)</strong></font> <br>
<br>
);<br>
end mip_device;<br>
<br>
architecture behav of mip_device is<br>
<br>
signal IO_in : std_logic_vector(15 downto 0);<br>
signal IO_out : std_logic_vector(15 downto 0);<br>
signal mip_clk_s : std_logic := '0';<br>
signal mip_clk_loss : std_logic := '0';<br>
signal mip_clk_loss_det : std_logic := '0';<br>
signal buf_overrun_s : std_logic := '0';<br>
signal buf_overrun_det : std_logic := '0';<br>
signal mip_raddr_s : std_logic := '0';<br>
signal mip_raddr_det : std_logic := '0';<br>
signal mip_waddr_s : std_logic := '0';<br>
signal mip_waddr_det : std_logic := '0';<br>
signal buf_rdy_s : std_logic := '0';<br>
signal buf_rdy_det : std_logic := '0';<br>
<br>
begin<br>
<br>
mip_dev_proc: process( CLK, RESETn )<br>
<br>
-- local variables<br>
variable mip_ctrl_q : std_logic_vector(15 downto 0) := x"0000";<br>
variable <strong>status_q</strong> : std_logic_vector(15 downto 0) := x"8000";<br>
variable addr : std_logic_vector(7 downto 0) := "00000000";<br>
variable i : integer range 0 to 255 := 0;<br>
variable interrupt : std_logic := '0';<br>
variable buf_dirty : std_logic := '0';<br>
variable msg_dirty : std_logic := '0';<br>
variable msg : mip_buf_t;<br>
<br>
begin<br>
if (RESETn = '0') then<br>
for i in 0 to 31 loop<br>
msg(i) := x"0000";<br>
end loop;<br>
i := 0;<br>
addr := "00000000";<br>
<font color="#ff0000"><strong>ioout <= status_q(15 downto 8);</strong></font><br>
status_q := x"8000";<br>
STATUS <= x"8000";<br>
<br>
if (LALE = '1') then<br>
addr := LADDR;<br>
end if;<br>
<br>
<br>
-- CPU WRITE<br>
if (LCS = '0') and (LWE = '0') then<br>
if (addr = status_addr) then<br>
-- Write to the MIP Status Register<br>
status_q := IO_in;<br>
ENABLE <= not(IO_in(15));<br>
elsif (addr = mbx_w1_addr) then<br>
-- Write to the MIP Mailbox Word 1 Register<br>
MBX_W1 <= IO_in;<br>
elsif (addr = mbx_w2_addr) then<br>
-- Write to the MIP Mailbox Word 2 Register<br>
MBX_W2 <= IO_in;<br><br>
else<br>
-- Set the Local Bus Write Address Error STATUS Bit (11)<br>
status_q(11) := '1';<br>
interrupt := '1';<br>
end if;<br>
end if;<br>
<br>
<br>
-- MIP Data Buffer Ready Rising Edge Detection<br>
if (buf_rdy_s = '1') and (buf_rdy_det = '0') then<br>
-- Set the MIP Buffer Ready STATUS Bit (5)<br>
status_q(5) := '1';<br>
interrupt := '1';<br>
if (msg_dirty = '0') then<br>
for i in 0 to 31 loop<br>
msg(i) := BUF(i);<br>
end loop;<br>
msg_dirty := '1';<br>
buf_dirty := '0';<br>
else<br>
-- Tell the MIP to hold-off.<br>
buf_dirty := '1';<br>
end if;<br>
end if;<br>
buf_rdy_det <= buf_rdy_s;<br>
<br>
<br>
-- MIP Data Buffer Overrun Rising Edge Detection<br>
if (buf_overrun_s = '1') and (buf_overrun_det = '0') then<br>
-- Set the MIP Data Buffer Overrun STATUS Bit (9)<br>
status_q(9) := '1';<br>
interrupt := '1';<br>
end if;<br>
buf_overrun_det <= buf_overrun_s;<br>
<br>
<br>
-- CPU READ<br>
if (LCS = '0') and (LOE = '0') then<br>
if (addr = status_addr) then<br>
<br>
<strong><font color="#ff0000">ioout <= status_q(15 downto 8);</font></strong><br>
<br>
-- Read the MIP Device Status Register<br>
IO_out <= status_q;<br>
elsif (addr = mbx_w1_addr) then<br>
-- Read the MIP Mailbox Word 1 Register<br>
IO_out <= MBX_W1;<br>
elsif (addr = mbx_w2_addr) then<br>
-- Read the MIP Mailbox Word 2 Register<br>
IO_out <= MBX_W2;<br>
elsif (addr = mbx_w3_addr) then<br>
-- Read the MIP Mailbox Word 3 Register<br>
IO_out <= MBX_W3;<br>
elsif (addr = mbx_w4_addr) then<br>
-- Read the MIP Mailbox Word 4 Register<br>
IO_out <= MBX_W4;<br>
elsif (addr = ctrl_addr) then<br>
-- Read the MIP Control Register<br>
IO_out <= mip_ctrl_q;<br>
else<br>
-- Convert addr to integer for indexing the Data Buffer<br>
i := to_integer( unsigned(addr) );<br>
if (i < status_id) then<br>
-- Read the Message Buffer<br>
IO_out <= msg(i);<br>
-- Check for the End Of Message Bit.<br>
if (msg(i)(14) = '1') then<br>
-- The entire Message has been read.<br>
if (buf_dirty = '1') then<br>
for i in 0 to 31 loop<br>
msg(i) := BUF(i);<br>
end loop;<br>
msg_dirty := '1';<br>
buf_dirty := '0';<br>
interrupt := '1';<br>
else<br>
msg_dirty := '0';<br>
end if;<br>
end if;<br>
else<br>
-- Set the Local Bus Read Address Error STATUS Bit (10)<br>
status_q(10) := '1';<br>
interrupt := '1';<br>
IO_out <= x"0000";<br>
end if;<br>
end if;<br>
end if;<br>
<br>
-- MIP Status Register READY Bit Logic:<br>
if ( (ENABLE = '0') or<br>
( (msg_dirty = '1') and (buf_dirty = '1') ) ) then<br>
status_q(0) := '0'; -- Drop the READY bit.<br>
else<br>
status_q(0) := '1';<br>
end if;<br>
STATUS <= status_q;<br>
<br>
<br>
if ((ENABLE = '1') and (interrupt = '1')) then<br>
-- Interrupt CPU when status changes:<br>
IRQ_OE <= '0'; -- Interrupt the CPU<br>
IRQn <= '0';<br>
interrupt := '0';<br>
else<br>
IRQ_OE <= '1';<br>
IRQn <= '1';<br>
end if;<br>
end if;<br>
end process; -- mip_dev_proc
I have code working on a hardware design that was compiled using Quartus Prime version 15.1. I installed QP version 17.1 and compiled the same code but the code did not work as expected. I have an IO port that was not being used (pins were assigned in top level entity) and added code (highlighted in red below) and recompiled in 17.1 and it seems to have "fixed" the code (very strange). I added the IO port to help debug the problem.<br>
<br>
I am not sure if it is an issue with the code or a compiler issue. Both compiler versions were used with default settings.<br>
<br>
Any help with understanding the compiler settings would be appreciated. (some code was deleted to fit here)<br>
<br>
entity mip_device is<br>
port<br>
(<br>
RESETn : in std_logic;<br>
CLK : in std_logic; -- Local Bus Clock<br>
ENABLE : inout std_logic; -- NOT(STATUS(15))<br>
<br>
<br>
-- Inputs from the Top Level Entity:<br>
MIP_CLK : in std_logic;<br>
<br>
<br>
-- Outputs to the MIP Bus (we can read them too):<br>
STATUS : inout std_logic_vector(15 downto 0);<br>
MBX_W1 : inout std_logic_vector(15 downto 0);<br>
MBX_W2 : inout std_logic_vector(15 downto 0);<br>
MBX_W3 : inout std_logic_vector(15 downto 0);<br>
MBX_W4 : inout std_logic_vector(15 downto 0);<br>
<br>
<br>
-- Inputs from the MIP Bus:<br>
CTRL : in std_logic_vector(15 downto 0);<br>
MIP_RADDR : in std_logic;<br>
MIP_WADDR : in std_logic;<br>
BUF_OVERRUN : in std_logic;<br>
BUF_RDY : in std_logic;<br>
BUF : in mip_buf_t;<br>
<br>
-- Inputs from the Local Bus:<br>
LCS : in std_logic; -- Local Bus Chip Select<br>
LALE : in std_logic; -- Local Bus Address Latch Enable<br>
LOE : in std_logic; -- Local Bus Output Enable<br>
LWE : in std_logic; -- Local Bus Write Enable<br>
LADDR : in std_logic_vector(7 downto 0);<br>
<br>
-- Outputs:<br>
IRQn : inout std_logic;<br>
IO : inout std_logic_vector(15 downto 0);<br>
IRQ_OE : out std_logic;<br>
<font color="#ff0000"><strong>ioout : out std_logic_vector(7 downto 0)</strong></font> <br>
<br>
);<br>
end mip_device;<br>
<br>
architecture behav of mip_device is<br>
<br>
signal IO_in : std_logic_vector(15 downto 0);<br>
signal IO_out : std_logic_vector(15 downto 0);<br>
signal mip_clk_s : std_logic := '0';<br>
signal mip_clk_loss : std_logic := '0';<br>
signal mip_clk_loss_det : std_logic := '0';<br>
signal buf_overrun_s : std_logic := '0';<br>
signal buf_overrun_det : std_logic := '0';<br>
signal mip_raddr_s : std_logic := '0';<br>
signal mip_raddr_det : std_logic := '0';<br>
signal mip_waddr_s : std_logic := '0';<br>
signal mip_waddr_det : std_logic := '0';<br>
signal buf_rdy_s : std_logic := '0';<br>
signal buf_rdy_det : std_logic := '0';<br>
<br>
begin<br>
<br>
mip_dev_proc: process( CLK, RESETn )<br>
<br>
-- local variables<br>
variable mip_ctrl_q : std_logic_vector(15 downto 0) := x"0000";<br>
variable <strong>status_q</strong> : std_logic_vector(15 downto 0) := x"8000";<br>
variable addr : std_logic_vector(7 downto 0) := "00000000";<br>
variable i : integer range 0 to 255 := 0;<br>
variable interrupt : std_logic := '0';<br>
variable buf_dirty : std_logic := '0';<br>
variable msg_dirty : std_logic := '0';<br>
variable msg : mip_buf_t;<br>
<br>
begin<br>
if (RESETn = '0') then<br>
for i in 0 to 31 loop<br>
msg(i) := x"0000";<br>
end loop;<br>
i := 0;<br>
addr := "00000000";<br>
<font color="#ff0000"><strong>ioout <= status_q(15 downto 8);</strong></font><br>
status_q := x"8000";<br>
STATUS <= x"8000";<br>
<br>
if (LALE = '1') then<br>
addr := LADDR;<br>
end if;<br>
<br>
<br>
-- CPU WRITE<br>
if (LCS = '0') and (LWE = '0') then<br>
if (addr = status_addr) then<br>
-- Write to the MIP Status Register<br>
status_q := IO_in;<br>
ENABLE <= not(IO_in(15));<br>
elsif (addr = mbx_w1_addr) then<br>
-- Write to the MIP Mailbox Word 1 Register<br>
MBX_W1 <= IO_in;<br>
elsif (addr = mbx_w2_addr) then<br>
-- Write to the MIP Mailbox Word 2 Register<br>
MBX_W2 <= IO_in;<br><br>
else<br>
-- Set the Local Bus Write Address Error STATUS Bit (11)<br>
status_q(11) := '1';<br>
interrupt := '1';<br>
end if;<br>
end if;<br>
<br>
<br>
-- MIP Data Buffer Ready Rising Edge Detection<br>
if (buf_rdy_s = '1') and (buf_rdy_det = '0') then<br>
-- Set the MIP Buffer Ready STATUS Bit (5)<br>
status_q(5) := '1';<br>
interrupt := '1';<br>
if (msg_dirty = '0') then<br>
for i in 0 to 31 loop<br>
msg(i) := BUF(i);<br>
end loop;<br>
msg_dirty := '1';<br>
buf_dirty := '0';<br>
else<br>
-- Tell the MIP to hold-off.<br>
buf_dirty := '1';<br>
end if;<br>
end if;<br>
buf_rdy_det <= buf_rdy_s;<br>
<br>
<br>
-- MIP Data Buffer Overrun Rising Edge Detection<br>
if (buf_overrun_s = '1') and (buf_overrun_det = '0') then<br>
-- Set the MIP Data Buffer Overrun STATUS Bit (9)<br>
status_q(9) := '1';<br>
interrupt := '1';<br>
end if;<br>
buf_overrun_det <= buf_overrun_s;<br>
<br>
<br>
-- CPU READ<br>
if (LCS = '0') and (LOE = '0') then<br>
if (addr = status_addr) then<br>
<br>
<strong><font color="#ff0000">ioout <= status_q(15 downto 8);</font></strong><br>
<br>
-- Read the MIP Device Status Register<br>
IO_out <= status_q;<br>
elsif (addr = mbx_w1_addr) then<br>
-- Read the MIP Mailbox Word 1 Register<br>
IO_out <= MBX_W1;<br>
elsif (addr = mbx_w2_addr) then<br>
-- Read the MIP Mailbox Word 2 Register<br>
IO_out <= MBX_W2;<br>
elsif (addr = mbx_w3_addr) then<br>
-- Read the MIP Mailbox Word 3 Register<br>
IO_out <= MBX_W3;<br>
elsif (addr = mbx_w4_addr) then<br>
-- Read the MIP Mailbox Word 4 Register<br>
IO_out <= MBX_W4;<br>
elsif (addr = ctrl_addr) then<br>
-- Read the MIP Control Register<br>
IO_out <= mip_ctrl_q;<br>
else<br>
-- Convert addr to integer for indexing the Data Buffer<br>
i := to_integer( unsigned(addr) );<br>
if (i < status_id) then<br>
-- Read the Message Buffer<br>
IO_out <= msg(i);<br>
-- Check for the End Of Message Bit.<br>
if (msg(i)(14) = '1') then<br>
-- The entire Message has been read.<br>
if (buf_dirty = '1') then<br>
for i in 0 to 31 loop<br>
msg(i) := BUF(i);<br>
end loop;<br>
msg_dirty := '1';<br>
buf_dirty := '0';<br>
interrupt := '1';<br>
else<br>
msg_dirty := '0';<br>
end if;<br>
end if;<br>
else<br>
-- Set the Local Bus Read Address Error STATUS Bit (10)<br>
status_q(10) := '1';<br>
interrupt := '1';<br>
IO_out <= x"0000";<br>
end if;<br>
end if;<br>
end if;<br>
<br>
-- MIP Status Register READY Bit Logic:<br>
if ( (ENABLE = '0') or<br>
( (msg_dirty = '1') and (buf_dirty = '1') ) ) then<br>
status_q(0) := '0'; -- Drop the READY bit.<br>
else<br>
status_q(0) := '1';<br>
end if;<br>
STATUS <= status_q;<br>
<br>
<br>
if ((ENABLE = '1') and (interrupt = '1')) then<br>
-- Interrupt CPU when status changes:<br>
IRQ_OE <= '0'; -- Interrupt the CPU<br>
IRQn <= '0';<br>
interrupt := '0';<br>
else<br>
IRQ_OE <= '1';<br>
IRQn <= '1';<br>
end if;<br>
end if;<br>
end process; -- mip_dev_proc
↧
Trouble populating memory from text file
Hello everyone, I need help populating my memory from a text file. Here is my RAM vhdl code:
and here is the text file:
I suspect that maybe there's an illegal (outside of the hex range) character in the .txt file but I don't see any. Maybe I need to save the text file in a different encoding format? Like ASCII or UTF-8?
Thanks everyone!
Code:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE STD.TEXTIO.ALL;
-- Add a generic parameter
ENTITY rem_ram IS PORT (
address : IN std_logic_vector(7 DOWNTO 0);
read_data : OUT std_logic_vector(31 DOWNTO 0)
);
END ENTITY rem_ram;
ARCHITECTURE rtl OF rem_ram IS
TYPE ram_type IS ARRAY(0 TO (2**address'LENGTH)-1) OF std_logic_vector(read_data'RANGE);
FUNCTION init_rom RETURN ram_type IS
VARIABLE r : ram_type;
BEGIN
FOR i IN r'RANGE LOOP
r(i) := (OTHERS => '0');
END LOOP;
RETURN r;
END FUNCTION;
-- FILL MEMORY FROM TEXT FILE
FUNCTION fill_memory RETURN ram_type IS
VARIABLE mem : ram_type;
TYPE HexTable IS ARRAY (CHARACTER RANGE <>) OF INTEGER;
CONSTANT lookup : HexTable('0' TO 'F'):=
(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, -1, -1, -1,
-1, -1, -1, -1, 10, 11, 12, 13, 14, 15);
FILE infile: text OPEN read_mode IS "mem_ram.txt";
VARIABLE buff: LINE;
VARIABLE addr_s: STRING(2 DOWNTO 1);
VARIABLE data_s : STRING(8 DOWNTO 1);
VARIABLE addr1, byte_cnt: INTEGER;
VARIABLE data: INTEGER RANGE 4294967295 DOWNTO 0;
BEGIN
WHILE (not endfile(infile)) LOOP
readline(infile, buff);
read(buff, addr_s);
read(buff, byte_cnt);
addr1 := lookup(addr_s(2))*16 + lookup(addr_s(1));
readline (infile, buff);
FOR i IN 1 TO byte_cnt LOOP
read(buff, data_s);
data := lookup(data_s(8))*268435456 + lookup(data_s(7))*16777216 + lookup(data_s(6))*1048576 +
lookup(data_s(5))*65536 + lookup(data_s(4))*4096 + lookup(data_s(3))*256 +
lookup(data_s(2))*16 + lookup(data_s(1));
mem(addr1) := CONV_STD_LOGIC_VECTOR(data, 32);
addr1 := addr1 + 1;
END LOOP;
END LOOP;
RETURN mem;
END FUNCTION;
SIGNAL ram : ram_type := fill_memory;
BEGIN
read_data <= ram(CONV_INTEGER(UNSIGNED(address)));
END ARCHITECTURE rtl;Code:
00
8C020000
04
8C030001
08
00430820
0C
AC010003
10
1022FFFF
14
1021FFFAThanks everyone!
↧
device tree source ehternet and skew timing => performance issue ?
hello,
i ve some problem with the network performance and the cyclone 5.
i try different kernel versions, after some error research i found
the solution it was/is the ethernet skew.
with the socfpga default device tree source, i get only ~10-40 Mbits/s with iperf.
i change the skew at the dts and the speed is now ~600Mbits/s.
Where can i get the skew settings?
i dont want to roll the dice.
we use an cylcone 5 with an micrel ksz9031 phy.
thanks for the support
i ve some problem with the network performance and the cyclone 5.
i try different kernel versions, after some error research i found
the solution it was/is the ethernet skew.
with the socfpga default device tree source, i get only ~10-40 Mbits/s with iperf.
i change the skew at the dts and the speed is now ~600Mbits/s.
Where can i get the skew settings?
i dont want to roll the dice.
we use an cylcone 5 with an micrel ksz9031 phy.
thanks for the support
↧
Linux font/cursor spacing problem.
Hi Everyone,
I am running Quartus Prime 17.1 Lite under Ubuntu 16.04 (64-bit). Everything seems to work properly except that I am experiencing a "spacing" problem with the cursor in the text editor. As I type, the cursor seems to move across the screen faster than the text. You would expect the cursor to always be just to the right of the last letter typed, and it is at the very left side of the editor. However, midway across the editor windows, the cursor is approximately 3 characters farther right than the last letter and by the right side of the editor window it is 6 characters off. I have tried launching Quartus with the "--internal_anti_aliasing" option, but it makes no difference. I have also tried different fonts and the amount of offset does change but is never correct. I don't notice such a problem in any other applications I have, just Quartus.
Has anyone else experienced this? Is there a remedy?
Thanks.
-Brian
I am running Quartus Prime 17.1 Lite under Ubuntu 16.04 (64-bit). Everything seems to work properly except that I am experiencing a "spacing" problem with the cursor in the text editor. As I type, the cursor seems to move across the screen faster than the text. You would expect the cursor to always be just to the right of the last letter typed, and it is at the very left side of the editor. However, midway across the editor windows, the cursor is approximately 3 characters farther right than the last letter and by the right side of the editor window it is 6 characters off. I have tried launching Quartus with the "--internal_anti_aliasing" option, but it makes no difference. I have also tried different fonts and the amount of offset does change but is never correct. I don't notice such a problem in any other applications I have, just Quartus.
Has anyone else experienced this? Is there a remedy?
Thanks.
-Brian
↧
↧
Read CHIP ID from JTAG
Is there a JTAG IR code that reads back the unique chip ID? I'm hoping to read the chip ID back with a code like this:
device_ir_shift -ir_value <CHIP-ID-IR> -no_captured_ir_value
device_dr_shift -length 64 -value_in_hex
Cheers,
device_ir_shift -ir_value <CHIP-ID-IR> -no_captured_ir_value
device_dr_shift -length 64 -value_in_hex
Cheers,
↧
PCIe Device Serial Number Extended Capability
Is there a way to support device serial number extended capability with Arria 10 PCIe? I'm hoping to send chip ID as device serial number to linux.
Cheers,
Cheers,
↧
Best suitable low cost Altera device supports OpenCL
Hi Everyone,
I am new for OpenCL FPGA platform. Please suggest me low cost Altera FPGA board which supports OpenCL completely.
I am new for OpenCL FPGA platform. Please suggest me low cost Altera FPGA board which supports OpenCL completely.
↧