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[SignalTap] -> how to merge SignalTap files?

March 10, 2018, 9:53 am
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Hi All,

Is it possible to merge several SignalTap files together (Quartus can load a single STP file only)?

When I disable an instance in the SignalTap file before the compilation, will this logic be not implemented (removed from SignalTap)?

Thank you!
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[SignalTap] -> how to merge SignalTap files?

March 10, 2018, 9:57 am
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Hi All,

Is it possible to merge several SignalTap files together (Quartus can load a single STP file only)?

When I disable an instance in the SignalTap file before the compilation, will this logic be not implemented (removed from SignalTap)?

Thank you!
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JTAG UART receive Integers from FPGA

March 10, 2018, 5:37 pm
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Dear community,

I'm trying to send some initialisation data to the FPGA and receive the results via JTAG UART.

The problem is that nios2-terminal, which I'm using to communicate with the JTAG UART IP core is text based, but I want to send and receive integers.

So I redirected StdIn and StdOut of nios2-terminal to my program and I send single Bytes to nios2-terminal.
Its a little tricky because when I send the byte 0x00 it terminates the string and the following bytes are all zero. So I wait after 0x00 until the Buffer is empty, which should be instantly because the FPGA should read much faster than I can write, but idk...
But except this problem, every byte I write to the nios2-terminal arrives at the FPGA without any losses or adding of bytes. Or maybe it does but not with the bytes in my initialisation data.

The other way around however, when I send a 0x0A which is the line feed character it adds a 0x0D which is the carriage return character. I can understand why it is that way and I can filter that out of my data afterwards. (Just to understand all my problems)

The real problem is when I try to send bytes like (0x9F, 0x9E, 0x91- 0x9C, ...) there comes something completely different. For example 0x9F arrives as 0x78 but for 0x78 it also arrives 0x78.
I can see what I send on SignalTap and I ran different tests, no timing issues. So i think its something nios2-terminal or the Ip core does.

Is there any alternative to nios2-terminal where I don't have all this trouble or does anyone know what I'm doing wrong, except from not using it how its supposed to be used?

Ps: I'm not using NiosII (lack of memory in my project), I access the IP core over the AVALON port, also not how its supposed to be
So why do I use JTAG UART at all? I'm seriously asking that myself. I thought it would be nice not to need a UART to USB adapter attached to my board and that it would be easy.
I'm working with the DE10-Lite devBoard with MAX10-10M50DAF484C7G FPGA and my PC is running on WIN10 (64bit)

I would be soooo happy if anyone could help me,
Thanks
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Max 10, how to "connect" to my on-chip-memory? which controller to use.

March 10, 2018, 10:21 pm
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Hi guys, I'm new in the fpga business, I have Max 10 for now.
I'm trying to understant how can I connect to my memory ,I know that I have only 64MB sdram.
Now, I read a lot online, in the ip catalog I saw sram controller and ssram controller , online I saw using of altsyncram exc,and Im lost, how do I know which one to use?

Thanks, a lot for your help,
Barak.
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MegaWizard Plug-In Manager didn't generate the .bsf file of IPCore

March 11, 2018, 6:55 am
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Hi, everyone.
I encountered a wierd trouble.
When I try to add a IPCore into the Block Diagram and generate an IP Core using MegaWizard Plug-In Manager, I got the following warning after the generator works out and said "MegaCore Function Generation successful."

The Warning said:"Block Symbol File xxxx.bsf is not generated from MegaWizard Plug-In Manager"

The version of Quartus is 13.3 Lite.

And I'm sure that the path of .bsf file don't contain any space.
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MegaWizard Plug-In Manager didn't generate the .bsf file of IPCore

March 11, 2018, 6:59 am
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Hi, everyone.
I encountered a wierd trouble.
When I try to add a IPCore into the Block Diagram and generate an IP Core using MegaWizard Plug-In Manager, I got the following warning after the generator works out and said "MegaCore Function Generation successful."
The Warning said:"Block Symbol File xxxx.bsf is not generated from MegaWizard Plug-In Manager"

The version of Quartus is 13.3 Lite
And I'm sure that the path of .bsf file don't contain any space.
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Can't scan JTAG chain - DE0-CV / Win 10

March 11, 2018, 8:18 pm
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Hello all,

I have purchased my first FPGA recently it is a DE0-CV. I cannot get my computer to access it via JTAG. I am using Windows 10.

- I have tried to use the DE0-CV Control Panel software in both RUN and PROG modes and it throws some error about JTAG.
-I have tried Quartus Prime 17.1 Lite in both Active Serial and JTAG mode and both of those in RUN and PROG.
- I have tried Quartus II 14.0 64bit Web Edition in both Active Serial and JTAG mode and both of those in RUN and PROG.

Does anyone have any suggestions? It is a brand new board and very frustrating to have this issue.
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How to add NEW counter Custom Qsys Components ?

March 12, 2018, 12:43 am
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Hello, i am a newbie, and having verilog counter code. I don`t know how to add "counter" as a NEW CUSTOM Qsys components?

module counter_qsys (
out , // Output of the counter
clk , // clock Input
);
input clk;
output [7:0] out;
reg [7:0] out=0;
//-- Sensitive to rising edge
always @(posedge clk) begin
//-- Incrementar el registro
out <= out+1;
end
endmodule

In qsys, i have clicked NEW component, and i got one pop-window. But in block "out" port is missing. I dont whether i am doing right or wrong. Please anyone guide me.
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How to run counter program in modelsim?

March 12, 2018, 2:06 am
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I am running following counter program without test bench. But in modelsim, i am not getting any signals. Please anyone share me counter examples program rar.

I want to run counter program either in Quartus or in NIOS. Please explain me how ?
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3 wire spi data transfer

March 12, 2018, 5:09 am
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Hi

I am using 3 wire SPI IP from the prime Software. I didn't found any document which says how to pass the data or how to use this IP.

In this IP,
Input side 3 wire SPI IP, which is Avalon memory mapped interface, consisting of data lines, clock, write, read, chipselect signals.
Output side 3 wire SPI IP, having SPI interface, consisting of MISO, MOSI, SS_N, SCLK.

I am using 5 slave to connect and communicate with 3 WIRE SPI.

CAN ANYONE HERE PLEASE TELL ME HOW TO PASS THE DATA OVER 3 WIRE SPI????
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What is Altera equivalent of Xilinx`s IBUF?

March 12, 2018, 5:18 am
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Hi,

Could someone tell if there is similar or equivalent in Altera of Xilinx`s IBUF?

Thanks
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DE10-standard ADV7180 read access

March 12, 2018, 9:44 am
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Hi,

I’m currently trying to develop logic that tries to read ADV7180 internal registers using the I2C interface (i.e., I2C_SCLK and I2C_SDAT) using PIN_Y24 and PIN_Y23. Looking at the schematics in the DE10-Standard.pdf document, I noticed that the I2C_SDAT doesn’t appear to be pulled up.

All the other I2C-related pins on the DE10-Standard board have pull-up resistors.

The FPGA demonstration example (DE10_Stanadard_TV) contains I2C logic connected to the FPGA_I2C_SDAT and FPGA_I2C_SCLK but, looking at the Verilog code, it appears that it only works for write access.

My question is, am I supposed to be able to do a I2C Read Access from the ADV7180 chip on the DE10-Standard board using the FPGA portion of the Cyclone V? Has anyone tried this with success?


Thanks,
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Timing violations with a reset signal

March 12, 2018, 10:17 am
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I created a global reset signal, which is active low.
Generating reset signal codes are from Reset_Delay.v as an example from Altera site.
(https://cloud.altera.com/devstore/pl...torage-design/)
For this module, I uses slowest clock(100Mhz) from a PLL.
But due to more faster clocks(2 shifted phase 250Mhz), I got some timing violations with that reset signals.
How can I remove these timing violations related to that reset signal?
Adding SDC? if yes, how to? or any other methods?

I use MAX10 device.
Please, help me.

Thanks
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Altera Pll error message. (Error: WTH!!!/n while executing "parse_tcl_data)

March 12, 2018, 2:42 pm
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I am trying to create a 1kHz output using cascaded clocks.

I however get this error message in both 17.0 and 17.1.

Error: WTH!!!/n while executing "parse_tcl_data $rule_name $reference_list" (procedure "my_set_rbc_check" line 21) invoked from within "my_set_rbc_check OUTPUT_CLOCK_FREQUENCY $param_args" (procedure "get_advanced_pll_legality_solved_legal_pll_values " line 21) invoked from within "get_advanced_pll_legality_solved_legal_pll_va lues $device_part $ref_clk [get_parameter_value output_clock_frequency$val] $fractional_vco_multiplier $c..." (procedure "validation_callback" line 264) invoked from within "validation_callback"

Here is what I have setup.
Any advice appreciated!

Thanks
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Using JTAG programmer with time limited evaluation IP license

March 12, 2018, 6:38 pm
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Hi,

I'm having some trouble programming my design using JTAG - specifically I cannot program my board with a time limited .SOF. I've tried this in SignalTap II firstly, which fails with "JTAG Chain Configuration: Programming failed". I figured maybe this had something to do with SignalTap II not working with time limited .sofs, so I tried programming in the Programmer, (under Finish Design in the Task window). I get similar results where I tell it to program, the dialog box comes up saying that the license is time limited, and then a notification that Progess: Failed.

What am I missing? As far as I know, I should be able to program the board to use the core indefinitely, as long as the board stays tethered via jtag. I think next I will try programming using quartus_pgm.exe rather than Quartus, but if anyone could provide any insight into this problem, I would appreciate it greatly.

I should note that my drivers etc all work fine, I've tested my setup with a design that does not include the Evaluation license IP, and JTAG programming that works fine.

Thanks for your time -
ap29
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LVDS signals transmitting and receiving Using I/O buffers

March 12, 2018, 11:51 pm
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Hello,

I have gone through lot of tutorials and am totally confused :confused:. I am new to Altera, so i don`t how to proceed with the design. Please anyone explain me how to start-up this design.

Task:

I need to give counter signals as LVDS signals. The LVDS signals should be transmitted to Cyclone V board. Please guide me.

Whether i can go for Block design using quartus IP core or how. If using Block design means, how to program my board. Need workflow of this process.
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how is the ds-5 debugger being called?

March 13, 2018, 12:23 am
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hey, i have a python script which supposed to open the ds-5 debugger and i'm not quite sure with what parameters i should call it:
i saw in one of the script at rocketboards this line:
Code:
"debugger --stop_on_connect=false --cdb-entry=\"" + CDB_ENTRY + "
it works but there are some bugs(like restore doesn't really work and sometimes it get stuck) so i'm thinking maybe i'm not opening it correctly.

i would like to know how is the debugger being opened in the ds-5, thanks.
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IP was not found in qsys

March 13, 2018, 12:35 am
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I'm using quartus prime lite edition 17.1 to open qsys. I open a correct design and there are some errors. The reason is " IP altera_pll was found in the ip catalog"

I don't know how to resolve it.
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Bidir Reset pin HPS nRST on 5CSEMA6F31I7N doen´t go low while POR

March 13, 2018, 12:49 am
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On our board with Cyclone V SoC 5CSEMA6F31I7N the bidirectional reset pin HPS nRST (C27) doen´t goes low while POR. We also see, when voltages fall below the POR threshold it takes several microseconds until the HPS IO-Pins changes to tristate. We have two boards that we can not contact with out Lauterbach Debugger. The boards have worked, on one board we have done some resets over the POR pin and some power on cycles.
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Qsys error:While creating NEW IP

March 13, 2018, 2:27 am
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Hi , I am trying to create a new component on Qsys using my verilog code in quartus. I am getting some errors [please look over the attachment], I don`t know how to fix it. Please guide me

Verilog code
Code:
module coun    (
 LED    ,  // Output of the counter
 clk    ,  // clock Input
 );
 input clk;
 output reg LED;
 reg [31:0] out=0; 
always @(posedge clk) begin
 out <= out + 1;
 LED=out[29];
end
endmodule
I need step-step training please
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