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migration from EPCQ to EPCQ-A

May 3, 2018, 2:54 am
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Hi,

on a custom board we have successfully used an altera Cyclone V (5CEBA2) with an EPCQ32 (ASx4).
Now we had to migrate from the EPCQ32 to the EPCQ32A.
We used Quartus Prime Lite 17.1.0 and 17.1.1 and programmed the EPCQ32A via the Quartus Programmer + USB blaster + SFL.
We followed the migration guideline AN822:
https://www.altera.com/documentation/tfb1498107381358.html

Compilation and download of the .jic file to the EPCQ32A are successful, but then the FPGA fails to load the configuration file at startup (CONF_DONE remains low).
We believe the hardware is fine (never had a problem with the EPCQ32).
(MSEL: 10011, nCE to GND, nSTATUS, nCONFIG, CONF_DONE with 10k pull-up to 3V3, six lines between the EPCQ32A and the FPGA (DATA[3..0], nCS, DCLK)

What we noticed in the map file is the following line:
Quad-Serial configuration device dummy clock cycle: 12

whereas the AN822 states:
Quote:
EPCQ—the dummy clock is configurable with the non-volatile configuration register (NVCR). When the EPCQ is used with a Cyclone® V, Arria® V or Stratix® V device, the dummy clock is configured to be 4, 10 or 12, depending on the byte-addressing mode and ASx1 or ASx4 configuration.
However, in EPCQ-A devices, the dummy clock is fixed at 8 and 6 for fast read and extended quad input fast read respectively. Therefore you must regenerate the programming files, such as .pof, .jic, and .rpd.
Is the dummy clock cycle wrong and is it the cause of our problem?
If this is our problem, how can we fix it? (we did not find any place where the dummy clock can be adjusted)

Or is the problem somewhere else? What else can we check?

Thanks for your help,
Regards
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input termination on ep4ce22f17c6(de0-nano terasic)

May 3, 2018, 5:18 am
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Hi! Can anybody explain how to enable input termination on ep4ce22f17c6(de0-nano terasic). I read quartus II handbook and cyclone IV handbook, but didn't find necessary information(may be read badly).
In .qsf I tried to write:

Code:
set_location_assignment PIN_A3 -to sdi_rx
set_instance_assignment -name IO_STANDARD LVDS -to sdi_rx
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sdi_rx


and had error

Error (169006): I/O pin "sdi_rx" specifies a Termination logic option setting of Differential, which is not supported by the device

May be ep4ce22f17c6 doesn't support input termination?
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Cyclone V AS configuration using Micron MT25Q

May 3, 2018, 7:37 am
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I have a card with aCyclone V that is using Active Serial Configuration from a Micron N25Q(128Mbit) flash.
Recently i have hadto switch flash to Micron MT25Q, due to the fact that N25Q is end-of-life.

The problem I havenow is that the FPGA on some of my boards does not configure, whereas it isalways configuring ok on other boards.

On the boards thatdo not configure properly, the configuration works ok if I put a probe on theflash clock, or if I solder on a 10pF capacitor between the flash clock andground, or if the board is warmed up.
So it seems to be atiming problem on the interface between the flash and the FPGA.

The FPGA is clockingdata out on the falling edge of the clock, and in on the falling edge of theclock.
The flash isclocking data out on the falling edge of the clock, and in on the rising edgeof the clock.

The clock frequencyis 9.8 MHz, so there should be no problem meeting setup times.
However, there couldbe a problem with hold time on data going from flash to FPGA, given that datais clocked out on falling edge from the flash, and clocked into the FPGA on thefalling edge.
But - the clock iscoming from the FPGA, the flash has a clock to out of at least 1.5ns (measuredvalue in lab is 2-2.5ns), and the FPGA has a hold time of 0ns, according to theCyclone V data sheet.

The clock looksbeautiful - perfect flanks, very little noise.
There is no noise onany of the power rails.

When the FPGA is notconfiguring, I see that CONF_DONE stays low, but nSTATUS is pulled low every~3.7ms.

I'm familiar withthis very nice thread: https://alteraforum.com/forum/showth...t=56762&page=4.
This thread hastempted me to use Windbond flash instead of Micron, but I'm concerned that thismay not improve my situation.
After all, theproblems I'm having is only on some of my boards, not on all of them.

I'm also aware thatAltera has recently added support for Micron MT25, but unfortunately this onlyapplies to 256Mbit and above, and at the moment these devices are hard to get.

So, I'm reaching outto all of you experts in this forum; do you have any suggestions, ideas,thoughts, comments?
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DE10-NANO - NIOS+ADC+DMA+ONCHIP MEMORY+HDMI on Platform Designer

May 3, 2018, 8:43 am
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Hello everyone, I'm new with FPGA, NIOS2 and Platform Designer and I have the DE10-nano board. As a project, I want to make a digital oscilloscope (a simple one at first).

I have Quartus Prime Lite Edition 17.1 and Nios II SBT.

The project consists on the following steps as I see it:
1. Sample 12-bit data from ADC channel 0.
2. Get the sampled data from the ADC to the on-chip memory through a DMA.
3. Show on LCD connected through HDMI a waveform made from the data saved on the on-chip memory.

Everything is controlled from a NIOS II Processor.


I've been using the ADC demonstration provided by terasIC to sample data from channel 0 (only one channel) successfully.

I tried adding a DMA controller and a On-chip memory to the Platform Designer to get all the sampled data from the ADC to the memory without success.

If someone can shed some light I would really appreciate that.

Hope I didn't miss any important information.

Thank you very much in advance
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PCIe IP Upstream switch capability

May 3, 2018, 8:48 am
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Can we use Altera Arria 10/Stratix 10 PCe hard ip to configure as PCIe upstream switch port?
I had read the spec and dont specify that.
Does anyone double confirm or guide/help me that is there is some way to use it as PCIe upstream switch port.
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Simulation stops before simtime

May 3, 2018, 10:57 am
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Any ideas why a simulation would stop early? When I run the simulation, scopes show the full simtime. However, after about 2-15% of the simtime, simulation will stop. If I keep the simtime the same and simulate again, it will stop at the same number of cycles. If I reduce or increase the simtime, it will still stop at a different percentage. I have two models in my project. The other runs as expected.

simtime = 36000 stops at T=2962
simtime = 299600 stops at T=6062

I'm using start time of 0 and stop time of simtime. Solver is set to Fixed-step discrete.

Any input would be appreciated!
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Where are older versions of Quartus located?

May 3, 2018, 6:21 pm
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Hi folks.

I plan on working with tutorials and demos that sometimes use older versions of Quartus.

I have Quartus Prime Lite installed, but am looking for the older versions to install. All I have found are Quartus Prime. Could someone point out the location of older versions of Quartus?

Thanks,
Bob
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problem on designing lfsr prng with implement the concept of bbs prng

May 4, 2018, 12:49 am
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Greeting, i am designing a lfsr prng, since my FYP supervisor has advise me to include some concept of bbs prng into it
i want to add on a security bits code output for each of my random number output
i had modified my coding but there are some problem i am facing and i dont know how to solve it, i had attached my output waveform

below is my modified VHDL coding:

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.lfsr_pkg.all;

entity lfsr1 is
port (
reset : in std_logic;
clk : in std_logic;
en : in std_logic;
count : out std_logic_vector (LFSR_W-1 downto 0); -- lfsr output
sc : out std_logic_vector (LFSR_W-1 downto 0)
);
end entity;


architecture rtl of lfsr1 is
signal count_i : std_logic_vector (LFSR_W-1 downto 0);
signal feedback : std_logic;



begin


-- option for LFSR size 11
feedback <= not(count_i(LFSR_W-1) xor count_i(LFSR_W-3));


sr_pr : process (clk)

variable sc1:std_logic_vector (LFSR_W-1 downto 0);
variable sc2:std_logic;
variable r:std_logic_vector(LFSR_W-1 downto 0);

begin
if (rising_edge(clk)) then
if (reset = '1') then
count_i <= (others=>'0');
elsif (en = '1') then
count_i <= count_i(LFSR_W-2 downto 0) & feedback;

for i in 0 to LFSR_W-1 loop
sc1:=count_i;
if sc1=1 then
sc2:='1';
else sc2:='0';
end if;
r(9):=r(10);
r(8):=r(9);
r(7):=r(8);
r(6):=r(7);
r(5):=r(6);
r(4):=r(5);
r(3):=r(4);
r(2):=r(3);
r(1):=r(2);
r(0):=r(1);
r(10):=sc2;
sc <= r;
end loop;
end if;
end if;
end process sr_pr;
count <= count_i;

end architecture;



Testbench:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use std.textio.all;
use work.lfsr_pkg.all;

entity tb_lfsr1 is
end entity;


architecture test of tb_lfsr1 is


constant PERIOD : time := 10 ns;
constant log_file: string := "res.log";


signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal en : std_logic := '0';
signal count : std_logic_vector (LFSR_W-1 downto 0);
signal sc : std_logic_vector (LFSR_W-1 downto 0);
signal endSim : boolean := false;


component lfsr1 is
port (
reset : in std_logic;
clk : in std_logic;
en : in std_logic;
count : out std_logic_vector (LFSR_W-1 downto 0);
sc : out std_logic_vector (LFSR_W-1 downto 0)
);
end component;


begin
clk <= not clk after PERIOD/2;
reset <= '0' after PERIOD*10;


-- Main simulation process
main_pr : process
begin
wait until (reset = '0');
wait until (clk = '1');
wait until (clk = '1');
wait until (clk = '1');
en <= '1';
for i in 0 to 7 loop
wait until (clk = '1');
end loop;
en <= '0';
wait until (clk = '1');
en <= '1';
while (not endSim) loop
wait until (clk = '1');
end loop;
end process main_pr;


-- End the simulation
stop_pr : process
begin
if (endSim) then
assert false
report "End of simulation."
severity failure;
end if;
wait until (clk = '1');
end process stop_pr;


DUT : lfsr1
port map (
clk => clk,
reset => reset,
en => en,
count => count,
sc => sc
);


-- Save data to file
save_data_pr : process
file file_id: text;
variable line_num: line;
variable cnt: integer := 0;
begin
-- Open the file
file_open(file_id, log_file, WRITE_MODE);
wait until (reset = '0' and en = '1');
wait until (clk = '1');

-- Loop and write all values to a file
for cnt in 0 to 2048*2-1 loop
write(line_num, to_integer(unsigned(count)) );
writeline(file_id, line_num);
wait until (en = '1' and clk = '1');
end loop;

file_close(file_id);
endSim <= true;
wait until (clk = '1');


end process save_data_pr;


end architecture;



i found that my security bits code just generated single output and then the rest were 0
please anyone can help me to look into the problem and teach me how to modify?
appreciate for your helping

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MEN F210, Cyclone II and Linux

May 4, 2018, 2:38 am
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Hello everybody,
I'm trying to get data from the GPS of a board, a MEN F210 [1]. The board is installed in an industrial case and I have Debian 9 installed with kernel 4.15. Altera modules of vanilla kernel are compiled and I can see the FPGA being recognized at startup but I can't see the UART device. The FPGA seems in state unknow.

How do I start the FPGA? I don't have a firmware or anything. I have the MEN tools that should allow me to build the drivers [2] but the software is old and can't make it work (have an Ubuntu 15.04 for that which seems the latest officially supported byt the toolkit).

Can anyone give me a hint? I'm surely missing something.

Thanks

[1] https://www.men.de/products/discontinued-products/f210/
[2] https://www.men.de/software/13z025-90/
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QUESTION on Signal Assignment of same signal and measuring times in FPGA.

May 4, 2018, 4:33 am
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Dear all,
can you tell me if the following is an illegal statement in VHDL 2008. I want to count up a signal read_pointer synchronously but I am not sure if the signal assignment of the same signa plus 1 will correctly synthesized:

Code:
       
address_pointer : process(CLK, RESET_H)
begin
    if (RESET_H = '0') then
        read_pointer <= (others => '0');
        elsif (rising_edge(CLK)) then
                read_pointer <= read_pointer + '1';
        end if;
end process address_pointer;
Or do I have to make a buffering signal like this read_pointer <= read_pointer_mem + 1 and then behind the process read_pointer_mem <= read_pointer?


And I do have one further question:

What is the best way to measure a span of time in FPGA. I want to measure the span of time between two data packets. My idea was to count just the clk_cycles between the packets. Are the other ways?

Thank you.
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Cyclone V ASx4 configuration

May 4, 2018, 7:20 am
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I've got a Terasic Cyclone V GX development board. I removed the EPCQ256 configuration device and am testing another alternative (Micron MT25QL256ABA). I created a simple project with LEDS and "generic_quad_spi_controlelr2" and am using JTAG indirect programming to program the device (jic file).

Quartus (17.1) will program the device without error. When I created the jic in "Active serial" mode it is able to boot but in "Active Serial x4" it isn't.

Any thoughts?
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MAX10 RSU: Dual Config IP vs User Logic

May 4, 2018, 7:58 am
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What are the Pros and Cons of using User Logic versus the Dual Configuration IP core to access the MAX10 RSU? Size? Capabilities? Are there cases where one is preferred over the other?

Thanks
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I have an 32DVRESOC3- ESOC3 need external power supply help ?

May 4, 2018, 1:32 pm
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Hello I'm currently enrolled in school and my new class requires the use of the esoc board for my labs. I have this board from my previous course I took about 2 years ago but cant find the power supply and can't seem to find info online as to power supply specs or where to get it from. Can any one here help ?
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Programming DE1-SoC FPGA only from Quartus Prime Lite Edition Ubuntu 16.04

May 4, 2018, 3:45 pm
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Hello, I am trying to simply program my CycloneV FPGA on the DE1-SoC board from Quartus Prime Lite in Ubuntu 16.04. I cannot seem to get it to work. The user guide says to do an auto-detect from the hardware programmer but the option is greyed out.

I have also changed the USB configs in /etc/udev/rules.d/90-usbblaster.rules


# USB-Blaster
BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6001", MODE="0666"
BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6002", MODE="0666"
BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6003", MODE="0666"


# USB-Blaster II


BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6010", MODE="0666"
BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6810", MODE="0666"


I still can not seem to find a way to get this thing programmed.
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Cyclone V: connecting multiple slaves via Avalon MM interface to HPS

May 4, 2018, 4:06 pm
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Hello all,
I am using the DE0-Nano-SoC kit, where the Cyclone V FPGA is located and Quartus Prime Version 17.1.0 software. I have a problem with the PLL reprogrammable configuration using the Avalon MM interface. I'm guessing that the problem is with the Avalon MM interface configuration. Can I connect several slaves directly to 'h2f_lw_axi_master' port of 'Cyclone V Hard Processor System' or should I use some intermediate IPcore for this? Below I attach screenshots from my platform designer's system, configuration of PLL block, content of registers, where should be PLL configuration, but I have strange things and my C-driver. I will be very grateful for any suggestions.

P.S. I checked the signals and my program does not stand in the reset or interrupt, and the 'locked' signal from the Altera PLL block is still in a high state. My input clock is 50MHz.

My C-driver for configuration of PLL:

Code:
#include <stdio.h>
#include <unistd.h>
#include <fcntl.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include "hwlib.h"
#include "soc_cv_av/socal/socal.h"
#include "soc_cv_av/socal/hps.h"
#include "soc_cv_av/socal/alt_gpio.h"
#include "hps_0.h"


/* Registers for PLL Reconfig*/


#define MODE              0x00
#define STATUS            0x01
#define START            0x02
#define N_COUNTER        0x03
#define M_COUNTER        0x04
#define C_COUNTER        0x05
#define DPS_COUNTER        0x06
#define FRAC_COUNTER    0x07
#define BS_COUNTER        0x08
#define CPS_COUNTER        0x09
#define C0_COUNTER        0x0A
#define C1_COUNTER        0x0B


#define MAPPED_SIZE (RECONFIG_SLOW_CLK_SPAN+IPCORE_GPIO_0_SPAN)


static void write_reg(unsigned int base, unsigned int offset, unsigned int val){
        volatile unsigned int* reg;
        reg = (unsigned int*)(base + offset);
        *reg = val;
}
static unsigned int read_reg(unsigned int base, unsigned int offset){
        volatile unsigned int* reg;       
        reg = (unsigned int*)(base + offset);
        return *reg;
}


int main() {
   
    printf("\nDate: %s ; Time: %s\n\n", __DATE__, __TIME__);
    void *virtual_base;
    int fd, i;
    int counter = 0xFFFF0000;
    unsigned int reg;


    if( ( fd = open( "/dev/mem", ( O_RDWR | O_SYNC ) ) ) == -1 ) {
        printf( "ERROR: could not open \"/dev/mem\"...\n" );
        return( 1 );
    }
   
    virtual_base = mmap(NULL, MAPPED_SIZE, ( PROT_READ | PROT_WRITE ), MAP_SHARED, fd, 0x0);
    if(virtual_base == MAP_FAILED) {
        printf( "ERROR: mmap() failed!\n" );
        close( fd );
        return( 1 );
    }
   
    unsigned int base_addr_gpio = (unsigned int) (virtual_base + IPCORE_GPIO_0_BASE);
    unsigned int base_addr_clk = (unsigned int) (virtual_base + RECONFIG_SLOW_CLK_BASE);
   
    printf("Simulation of GPIO:\n\n");
    //simulate GPIO
    for(i = 0; i < 64; i++ ){
        write_reg(base_addr_gpio, 0x0, counter);
        reg = read_reg(base_addr_gpio, 0x0);
        printf("Memory content: 0x%x\t Number loop: %d\n", reg, i);
        counter=counter+1;
    }
   
    printf("\nConfiguration of PLL:\n\n");
   
    //configuration PLL to 1 MHz
    // f_ref = (f_in/n) = 50MHz / 1 = 50 MHz => (f_ref range: 50-800 MHz!)
    // f_out = ((f_ref * M)/C)
    // 1MHz = ( 50 MHz *1)/50 )
    write_reg(base_addr_clk, MODE, 0b1); // polling mode
    reg = read_reg(base_addr_clk, MODE);
    printf("MODE of PLL: 0x%x\n", reg);
   
    write_reg(base_addr_clk, M_COUNTER, 0x0001); // M = 1
    reg = read_reg(base_addr_clk, M_COUNTER);
    printf("M_COUNTER of PLL: 0x%x\n", reg);
   
    write_reg(base_addr_clk, FRAC_COUNTER, 0x000000);
   
    write_reg(base_addr_clk, N_COUNTER, 0x0001); // N = 1
    //write_reg(base_addr_clk, N_COUNTER, 0x10000); // N -> bypass enable (f_ref = f_in)
    reg = read_reg(base_addr_clk, N_COUNTER);
    printf("N_COUNTER of PLL: 0x%x\n", reg);
   
    write_reg(base_addr_clk, C_COUNTER, 0x00A06); // C = 50 (0x19+0x19) -> set C0
   
    reg = read_reg(base_addr_clk, C_COUNTER);
    printf("C_COUNTER of PLL: 0x%x\n", reg);
   
    write_reg(base_addr_clk, C_COUNTER, 0x4060E); // C = 50 (0x19+0x19) -> set C1
   
    reg = read_reg(base_addr_clk, C_COUNTER);
    printf("C_COUNTER of PLL: 0x%x\n", reg);
   
    write_reg(base_addr_clk, BS_COUNTER, 0x6); // medium bandwidth
    reg = read_reg(base_addr_clk, BS_COUNTER);
    printf("BS_COUNTER of PLL: 0x%x\n", reg);
   
    write_reg(base_addr_clk, CPS_COUNTER, 0x2);
    reg = read_reg(base_addr_clk, CPS_COUNTER);
    printf("CPS_COUNTER of PLL: 0x%x\n", reg);
   
    write_reg(base_addr_clk, START, 0b1);
   
    sleep(1);


    reg = read_reg(base_addr_clk, M_COUNTER);
    printf("\nM_COUNTER of PLL: 0x%x\n", reg);
    reg = read_reg(base_addr_clk, N_COUNTER);
    printf("N_COUNTER of PLL: 0x%x\n", reg);
    reg = read_reg(base_addr_clk, C_COUNTER);
    printf("C_COUNTER of PLL: 0x%x\n", reg);
    reg = read_reg(base_addr_clk, C0_COUNTER);
    printf("C0_COUNTER of PLL: 0x%x\n", reg);
    reg = read_reg(base_addr_clk, C1_COUNTER);
    printf("C1_COUNTER of PLL: 0x%x\n", reg);


    reg = read_reg(base_addr_clk, STATUS);
    printf("Status of PLL: 0x%x\n", reg);
   
    if(reg != 0x01)
        printf("Unfortunately PLL is not correctly configured\n\n");
    else
        printf("Successful: PLL is correctly configured\n\n");
               
    if(munmap(virtual_base, MAPPED_SIZE) != 0){
        printf( "ERROR: munmap() failed...\n" );
        close( fd );
        return( 1 );
    }


    close( fd );


    return( 0 );
}


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configure the triple speed ethernet register with verilog

May 5, 2018, 1:29 am
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Hello! I am using TSE(triple speed ethernet) ip core to implement communication bewteen my pc and the FPGA board(cyclone IV). But I don't know how to configure the TSE register with verilog. I do read some information from the user guide. For example, here are from the user guide:


Base registers to configure the MAC function. At the minimum, you must
configure the following functions:
• Primary MAC address (mac_0/mac_1)
• Enable transmit and receive paths (TX_ENA and RX_ENA bits in the
command_config register)


But I don't know how to realize this configuration in my quartus II project with verilog.
Anything can be help!
Best wishes!
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RTL synthesis diagram

May 5, 2018, 9:11 am
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Hi,

Where can i find the RTL synthesis diagram of the compiled kernel?

Thanks
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login from two PCs fails on one pc, password is same...

May 5, 2018, 11:26 am
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Hi all. Does it make sense that i can log in one computer with my password, but conneot log in on another at the same time, using same password? When i log in on the second PC i get message 'Authentication failed, please try again;'. I have tried resetting passwrod a few times - with password reset request coming from either machine gets the same result. thanks. (I have successfully logged on from both PCs as recently as two days ago)
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Quartus 2 and .LVDS

May 5, 2018, 12:38 pm
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I have an easy question for one of the experts. I am using Quartus 2 13.1 and trying to program a Terasic DE3. This is the board with the 4 HSTC connectors, connected to the pads that support LVDS. Here's what I did:

In Verilog I instantiate an input that will come in as LVDS, and an output that goes out single ended on a QPIO pin (to be viewed on a logic analyzer) in the top level module top.v

module top (
output qpio,
input top
);


assign qpio = top;
endmodule

I then select Processing/Start/Start Analysis & Elaboration and then go into the Pin Planner. I set the pin for the input pin "top" to a legitimate differential pin, and set the I/O Standard to LVDS. The Pin Planner automatically inserts the negative pair for that pin also as LVDS, which is what I expect. I also select the pin for "qpio" as 3.3V. So far so good.

When I compile it, it works fine. However, I also want to set the internal resistance to 100 Ohms. So I look in the Pin Planner, and there's a column called "Input Termination", which looks promising, but when I click on it to see what the options are, all I see are things like "Off", "Parallel 50 Ohm with Calibration", then a bunch of "Series 25 Ohms..." options, 40, 50, and 60, but that's it, nothing that says "100 Ohms" or the option "Differential", which is what I had expected. How do I get it to put 100 Ohms across the pair?

Also, is it correct that I do not need to instantiate a differential IO buffer in my Verilog? I'm assuming that is the case, since there is no "n" input to route to it anyway.
↧

Constraining LEDs/Switches to VHDL onDE1-SoC

May 5, 2018, 4:06 pm
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Hello, I am trying to write some basic VHDL that "slide" an on led down the 10 leds on the DE1-SoC board. I have loaded the .sof onto the board but nothing is lighting up. I think the VHDL is good because I have compiled and loaded it onto a Xilinx board. I am guessing the issue is with the .sdc or .qsf files which I am given to understand constrain the code to the on-board hardware. I will post the VHDL, the .sdc, and the .qsf.

led_slide.vhd
Code:
library ieee;use ieee.std_logic_1164.all;


entity led_slide is
  port(
    clk:    in std_logic;
    sel:    in std_logic;
    z:        out std_logic_vector(9 downto 0)
  );
end led_slide;


architecture Behavioral of led_slide is
  type my_state is (
    s0,
    s1,
    s2,
    s3,
    s4,
    s5,
    s6,
    s7,
    s8,
    s9
  );
  signal n_s: my_state;
  signal clk_div:    std_logic;
begin
  process(clk_div)
  begin
    if clk_div='1' and clk_div'event then
      case n_s is
        when s0 =>
          z <= "1000000000";
          if sel='1' then
              n_s <= s1;
          else
              n_s <= s9;
          end if;
        when s1 =>
          z <= "0100000000";
          if sel='1' then
              n_s <= s2;
          else
              n_s <= s1;
          end if;
        when s2 =>
          z <= "0010000000";
          if sel='1' then
              n_s <= s3;
          else
              n_s <= s1;
          end if;
        when s3 =>
          z <= "0001000000";
          if sel='1' then
              n_s <= s4;
          else
              n_s <= s2;
          end if;
        when s4 =>
          z <= "0000100000";
          if sel='1' then
              n_s <= s5;
          else
              n_s <= s3;
          end if;
        when s5 =>
          z <= "0000010000";
          if sel='1' then
              n_s <= s6;
          else
              n_s <= s4;
          end if;
        when s6 =>
          z <= "0000001000";
          if sel='1' then
              n_s <= s7;
          else
              n_s <= s5;
          end if;
        when s7 =>
          z <= "0000000100";
          if sel='1' then
              n_s <= s8;
          else
              n_s <= s6;
          end if;
        when s8 =>
          z <= "0000000010";
          if sel='1' then
              n_s <= s9;
          else
              n_s <= s7;
          end if;
        when s9 =>
          z <= "0000000001";
          if sel='1' then
              n_s <= s0;
          else
              n_s <= s8;
          end if;
      end case;
    end if;
  end process;


  process(clk)
    variable count: integer;
  begin
    if clk='1' and clk'event then
      if count=99999 then
          clk_div <= not clk_div;
          count := 0;
      else
          count := count + 1;
      end if;
    end if;
  end process;
end Behavioral;
de1soc_master.qsf
Code:

set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEMA5F31C6
set_global_assignment -name TOP_LEVEL_ENTITY "DE1_SoC"
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name SDC_FILE led_slide.sdc

##============================================================
## LEDR
##============================================================
set_location_assignment PIN_V16 -to z[0]
set_location_assignment PIN_W16 -to z[1]
set_location_assignment PIN_V17 -to z[2]
set_location_assignment PIN_V18 -to z[3]
set_location_assignment PIN_W17 -to z[4]
set_location_assignment PIN_W19 -to z[5]
set_location_assignment PIN_Y19 -to z[6]
set_location_assignment PIN_W20 -to z[7]
set_location_assignment PIN_W21 -to z[8]
set_location_assignment PIN_Y21 -to z[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[9]
#
led_slide.sdc
Code:
#**************************************************************
# Altera DE1-SoC SDC settings
# Users are recommended to modify this file to match users logic.
#**************************************************************


#**************************************************************
# Create Clock
#**************************************************************
create_clock -period 20 [get_ports CLOCK_50]
create_clock -period 20 [get_ports CLOCK2_50]
create_clock -period 20 [get_ports CLOCK3_50]
create_clock -period 20 [get_ports CLOCK4_50]


create_clock -period "27 MHz"  -name tv_27m [get_ports TD_CLK27]

# VGA : 640x480@60Hz
create_clock -period "25.18 MHz" -name clk_vga [get_ports VGA_CLK]

#**************************************************************
# Create Generated Clock
#**************************************************************
derive_pll_clocks


#**************************************************************
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty

#**************************************************************
# Set Input Delay
#**************************************************************
# Board Delay (Data) + Propagation Delay - Board Delay (Clock)
set_input_delay -max -clock clk_dram -0.048 [get_ports DRAM_DQ*]
set_input_delay -min -clock clk_dram -0.057 [get_ports DRAM_DQ*]


set_input_delay -max -clock tv_27m 3.692 [get_ports TD_DATA*]
set_input_delay -min -clock tv_27m 2.492 [get_ports TD_DATA*]
set_input_delay -max -clock tv_27m 3.654 [get_ports TD_HS]
set_input_delay -min -clock tv_27m 2.454 [get_ports TD_HS]
set_input_delay -max -clock tv_27m 3.656 [get_ports TD_VS]
set_input_delay -min -clock tv_27m 2.456 [get_ports TD_VS]


#**************************************************************
# Set Output Delay
#**************************************************************
# max : Board Delay (Data) - Board Delay (Clock) + tsu (External Device)
# min : Board Delay (Data) - Board Delay (Clock) - th (External Device)
set_output_delay -max -clock clk_dram 1.452  [get_ports DRAM_DQ*]
set_output_delay -min -clock clk_dram -0.857 [get_ports DRAM_DQ*]
set_output_delay -max -clock clk_dram 1.531 [get_ports DRAM_ADDR*]
set_output_delay -min -clock clk_dram -0.805 [get_ports DRAM_ADDR*]
set_output_delay -max -clock clk_dram 1.533  [get_ports DRAM_*DQM]
set_output_delay -min -clock clk_dram -0.805 [get_ports DRAM_*DQM]
set_output_delay -max -clock clk_dram 1.510  [get_ports DRAM_BA*]
set_output_delay -min -clock clk_dram -0.800 [get_ports DRAM_BA*]
set_output_delay -max -clock clk_dram 1.520  [get_ports DRAM_RAS_N]
set_output_delay -min -clock clk_dram -0.780 [get_ports DRAM_RAS_N]
set_output_delay -max -clock clk_dram 1.5000  [get_ports DRAM_CAS_N]
set_output_delay -min -clock clk_dram -0.800 [get_ports DRAM_CAS_N]
set_output_delay -max -clock clk_dram 1.545 [get_ports DRAM_WE_N]
set_output_delay -min -clock clk_dram -0.755 [get_ports DRAM_WE_N]
set_output_delay -max -clock clk_dram 1.496  [get_ports DRAM_CKE]
set_output_delay -min -clock clk_dram -0.804 [get_ports DRAM_CKE]
set_output_delay -max -clock clk_dram 1.508  [get_ports DRAM_CS_N]
set_output_delay -min -clock clk_dram -0.792 [get_ports DRAM_CS_N]


set_output_delay -max -clock clk_vga 0.220 [get_ports VGA_R*]
set_output_delay -min -clock clk_vga -1.506 [get_ports VGA_R*]
set_output_delay -max -clock clk_vga 0.212 [get_ports VGA_G*]
set_output_delay -min -clock clk_vga -1.519 [get_ports VGA_G*]
set_output_delay -max -clock clk_vga 0.264 [get_ports VGA_B*]
set_output_delay -min -clock clk_vga -1.519 [get_ports VGA_B*]
set_output_delay -max -clock clk_vga 0.215 [get_ports VGA_BLANK]
set_output_delay -min -clock clk_vga -1.485 [get_ports VGA_BLANK]
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