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cannot generate ddr3 core quartus 16.0

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I am having a frustrating issue where i am unable to generate a ddr3 core throught the ip catalog.

I configure the core i want in the ip catalog and when go to generate the generation wizard hangs

Info: ddr3_gen_0: Variation language : VHDL
Info: ddr3_gen_0: Output directory : C:\repos\ddr3_ref_design
Info: ddr3_gen_0: Generating variation file C:\repos\ddr3_ref_design\ddr3_gen_0.vhd
Info: ddr3_gen_0: Generating synthesis files
Info: Generating altera_mem_if_ddr3_emif "ddr3_gen_0" for QUARTUS_SYNTH
Info: "ddr3_gen_0" instantiated altera_mem_if_ddr3_emif "ddr3_gen_0"
Info: "ddr3_gen_0" instantiated altera_mem_if_ddr3_pll "pll0"
Info: Generating clock pair generator
Info: Generating altgpio
Info:
Info: *****************************
Info:
Info: Remember to run the ddr3_gen_0_p0_pin_assignments.tcl
Info: script after running Synthesis and before Fitting.
Info:
Info: *****************************
Info:
Info: "ddr3_gen_0" instantiated altera_mem_if_ddr3_phy_core "p0"
Info: "ddr3_gen_0" instantiated altera_mem_if_ddr3_afi_mux "m0"


The wizard never get past this point.....

I have tried this on quartus 15.0/16.0/17.1 on both lite and full versions of the software and it always hangs at this point...

I dont know what to do?

Any suggestions?

Thanks
Attached Images

Cyclone 10GX dev kit PCIe example

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I downloaded this example design for the Cyclone 10GX dev kit at:https://cloud.altera.com/devstore/pl...2151/download/


and extracted the archive. But if I load the enclosed sof file:


Code:

md5sum Cyclone10GX_PCIeGen2x4_DMA_17_1_2_restored/master_image/top.sof
726940bdd434031299372ceeb1cae16e  Cyclone10GX_PCIeGen2x4_DMA_17_1_2_restored/master_image/top.sof

And re-boot the PC in which the PCIe board is installed the PC will not even boot. It will not boot until I power cycle the PC (in which the loaded sof file disappears of course). I have no problems booting and enumerating using other PCIe boards inserted into the same PCIe slot on the PC. The PC has an Intel H270 Express chipset.


Did anybody else get the example PCIe design enumerated and accessible? Or even got the DMA example running?

OpenCL 15.1 vs 17.1 with DE1-SoC (Cyclone V SoC)

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Hi,

I have designed a circuit with OpenCL using Quartus 15.1 in DE1-SoC board, the resources utilisation was fine (about 53%), I take the same cl file and compile it with OpenCL using Quartus 17.1, it cannot fit on the device and it takes more than the existing resources on the FPGA (about 130%).

Is there any explications?
How can I resolve this problem?

Thanks

HLS on Quartus 15.1

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Hi,

I found some materials of HLS on Quartus 15.1 (/----/Altera/15.1/hld/Readme.pdf) but I can't found how it works

Is there any Idea about HLS with 15.1? I can't find this on internet.

Thnaks

[SVA] signal rise and stay stable -> how to write an assertion?

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Hi All,

How can I write an assertion for a signal, which should rise within between 10 to 20 cycles and stay stable (HIGH) until the assertion will be disabled?

Thank you!

Where can I get the package trace lengths for Cyclne IV GX ?

Some questions about intel HLS RTL design.

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Hello.


I am currently testing RTL design using Intel HLS. There are a number of errors that occur during HLS compilation and RTL conversion, but the error seems to lack work around or guide.
I'd like to ask you a few questions about this difficulty. This includes questions about HLS optimization errors and their own concepts.


- Is the intel HLS software for creating one independent RTL IP?
- Does a verilog top design with multiple sub-modules(instances) need to be designed manually? (I don't need to use SOPC or SOC. So, I also don't consider Qsys to design)
- Is it possible to obtain a generic sequential RTL design with HLS that does not include an Avalon interface? What is the exact purpose of the hls_always_run_component?
- The user manual says that the HLS/matrix_mult.h library for matrix multiplication is provided, but where is it located? Not found in Quaruts 17.1 standard and lite in use.
- Where can I find the meaning of error messages generated when converting the FPGA?
I got an error : Call parameter type does not match function signature! What does this mean?
Here's a code structure I've created. Please give me a lot of advice.

code: main.cpp

float (*function1(x,x,x))[3] {}
float (*function2(x,x,x))[3] {}
float (*function3(x,x,x))[3] {}

component float (*aaa())[2] {
float (*y1)[3] = function1(x,x,x);
float (*y2)[3] = function1(y1,x,x);
....
return y9;

int main() {
float (*aaa_out)[2] = aaa();
printf("%f\n", aaa_out[0][0]);
...
return 0;
}

Need helpl with DMA

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Hi everyone, i need help with using DMA in bare-metal project.

I have GHRD, and i need to transfer data (it just 0 to 127 count) from HPS RAM(as i understand from ftp://ftp.altera.com/up/pub/Intel_Ma..._from_FPGA.pdf , its address 0xffff0000) to FPGA OCRAM(its address 0xc0000000 in my system) using HPS DMA and then i show this data from FPGA OCRAM on LEDS(0xFF210040).

But something goes wrong, and when i show data on leds, i see only 0-3 ,but it must be 0-1-2-3-4-..127. And leds are blinks(i see 0-0-1-0-2-0-3), so i think it is zeros between 0 and 1, 1 and 2, 2 and 3,...
When i show on leds data direct from hps ram after initializing it, leds dont blink(i see 0-1-2-3-...-127)

I really dont understand why that happens and i spend 3 days , but i still dont know what i do wrong.

Please someone, help me to understand and fix it.



firstly, i setup dma:
Code:

ALT_STATUS_CODE socfpga_dma_setup(){
    printf("INFO: Setup DMA System ...\n");


    ALT_STATUS_CODE status = ALT_E_SUCCESS;


    if (status == ALT_E_SUCCESS)
    {
        // Configure everything as defaults.


        ALT_DMA_CFG_t dma_config;
        dma_config.manager_sec = ALT_DMA_SECURITY_DEFAULT;
        for (int i = 0; i < 8; ++i)
        {
            dma_config.irq_sec[i] = ALT_DMA_SECURITY_DEFAULT;
        }
        for (int i = 0; i < 32; ++i)
        {
            dma_config.periph_sec[i] = ALT_DMA_SECURITY_DEFAULT;
        }
        for (int i = 0; i < 4; ++i)
        {
            dma_config.periph_mux[i] = ALT_DMA_PERIPH_MUX_DEFAULT;
        }


        status = alt_dma_init(&dma_config);
        if (status != ALT_E_SUCCESS)
        {
            printf("ERROR: alt_dma_init() failed.\n");
        }
    }


    // Allocate the DMA channel


    if (status == ALT_E_SUCCESS)
    {
        status = alt_dma_channel_alloc_any(&channel);
        if (status != ALT_E_SUCCESS)
        {
            printf("ERROR: alt_dma_channel_alloc_any() failed.\n");
        }
        else
        {
            printf("INFO: Channel %d allocated.\n", (int)(channel));
        }
    }


    // Verify channel state


    if (status == ALT_E_SUCCESS)
    {
        ALT_DMA_CHANNEL_STATE_t state;
        status = alt_dma_channel_state_get(channel, &state);
        if (status == ALT_E_SUCCESS)
        {
            if (state != ALT_DMA_CHANNEL_STATE_STOPPED)
            {
                printf("ERROR: Bad initial channel state.\n");
                status = ALT_E_ERROR;
            }
        }
    }






    if (status == ALT_E_SUCCESS)
    {
        status = alt_dma_program_init(&program);
        if (status != ALT_E_SUCCESS)
        {
            printf("ERROR: alt_dma_program_init() failed.\n");
        }
        else
        {
            printf("INFO: Dma program_byffer initialized.\n");
        }
    }




    if (status == ALT_E_SUCCESS)
    {
        printf("INFO: Setup of DMA successful.\n\n");
    }
    else
    {
        printf("ERROR: Setup of DMA return non-SUCCESS %d.\n\n", (int)status);
    }


    return status;
}


then goes my main fuction:
Code:

ALT_STATUS_CODE dma_hpsram_to_fpgaram(){
    // Just base addresses of GHRD components
    const uint32_t ALT_LWFPGA_BASE        = 0xFF200000;
    const uint32_t ALT_LWFPGA_LED_OFFSET  = 0x00010040;


    const uint32_t ALT_H2F_BASE                = 0xc0000000;
    const uint32_t ALT_H2F_OCRAM_OFFSET      = 0x00000000;
    const uint32_t ALT_HPS_OCRAM              = 0xffff0000;


    // turn off leds
    alt_write_word(ALT_LWFPGA_BASE + ALT_LWFPGA_LED_OFFSET, 0);


    uint32_t temp=0;
    uint32_t offset=0;


    // write 0-127 to hps ram
    for (uint32_t i = 0; i < 128; ++i)
    {
        alt_write_byte(ALT_HPS_OCRAM+offset,temp);
        temp++;
        offset=offset+1;
    }


    // transfer data from hps ram to fpga ocram
    size_t size=128;
    uint32_t dst=ALT_H2F_BASE+ALT_H2F_OCRAM_OFFSET;
    uint32_t src=ALT_HPS_OCRAM;
    // this function i take from altera design examples (hps dma)
    dma_memory_to_memory(&src, &dst, size);


    // check result of transfer, looking at fpga ocram contents
    offset=0;
        for (uint32_t i = 0; i < 12800000; ++i)
        {
            if(i%100000==0)
            {
                // that big numbers for making leds switch less often
                alt_write_byte(ALT_LWFPGA_BASE+ALT_LWFPGA_LED_OFFSET, alt_read_byte(dst+offset));
                offset=offset+1;
            }
    }
    return ALT_E_SUCCESS;
}


it uses function from altera design examples( hps ram):
Code:

ALT_STATUS_CODE dma_memory_to_memory(void * src, void * dst, uint32_t size)
{
    ALT_STATUS_CODE status = ALT_E_SUCCESS;


    printf("INFO: Demo DMA memory to memory transfer.\n");


    // Copy source buffer over destination buffer
    if(status == ALT_E_SUCCESS)
    {
        status = alt_dma_memory_to_memory(channel, &program, dst, src, size, false, (ALT_DMA_EVENT_t)0);
    }


    // Wait for transfer to complete
    if (status == ALT_E_SUCCESS)
    {
        printf("INFO: Waiting for DMA transfer to complete.\n");
        ALT_DMA_CHANNEL_STATE_t channel_state = ALT_DMA_CHANNEL_STATE_EXECUTING;
        while((status == ALT_E_SUCCESS) && (channel_state != ALT_DMA_CHANNEL_STATE_STOPPED))
        {
            status = alt_dma_channel_state_get(channel, &channel_state);
            if(channel_state == ALT_DMA_CHANNEL_STATE_FAULTING)
            {
                ALT_DMA_CHANNEL_FAULT_t fault;
                alt_dma_channel_fault_status_get(channel, &fault);
                printf("ERROR: DMA CHannel Fault: %d\n", (int)fault);
                status = ALT_E_ERROR;
            }
        }
    }
    return status;
}


Matrix multiplication design example

Factory pin state value

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When i buy Altera FPGA (Cyclone V GX for example), solder it on board, and give right voltage to power pin, wich state of user I/O pin i must see ? I think Tri-stated? Can somebody show me official documentation where i can see this information?

State Machine: Fitter seems to have problems with many states

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Good day,

is there are recommendation for state machines with a bigger number of states? Seems to me that the fitter does seem to need dramatically more compile time for state machines above 27 states. (Attached Project. State machine in module ram_ip_control).
What I already tried:
- Turn Fitter Initial Place Seed to 8
- Enabled Register duplication.

Analysis and synthesis clearly recognized the state machine.
The design uses only 12% of LEs of Cyclone V, one pll, one hard ram controller and one dual port ram synthesized as ram and not as LE. I tried to set all nessesary timing constraints.
However fitter runs on 75 % CPU Usage for a long time and stays at 36 % completion.
Is there anything that I can do, to solve this issue.

Greetings
Attached Files

Running 2 different kernels on 2 different devices in Emulator mode.

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Hi,
I'm trying to configure 2 different kernels on 2 different devices in emulator mode. But not able to configure on 2nd device.
I could able to launch kernel1 on device1 properly. When I'm trying to launch 2nd kernel on 2nd device then it is throwing "Error in clEnqueueTask1 45" error.
Error no 45 = CL_INVALID_PROGRAM_EXECUTABLE.


Tried with the following code:


#define DEVICE_ID_1 1
#define DEVICE_ID_0 0

cl_program createProgramFromBinary(cl_context context, const char *binary_file_name, const cl_device_id *devices, unsigned num_devices)
{
// Early exit for potentially the most common way to fail: AOCX does not exist.
if(!fileExists(binary_file_name)) {
printf("AOCX file '%s' does not exist.\n", binary_file_name);
checkError(CL_INVALID_PROGRAM, "Failed to load binary file");
}

// Load the binary.
size_t binary_size;
scoped_array<unsigned char> binary(loadBinaryFile(binary_file_name, &binary_size));
if(binary == NULL) {
checkError(CL_INVALID_PROGRAM, "Failed to load binary file");
}

scoped_array<size_t> binary_lengths(num_devices);
scoped_array<unsigned char *> binaries(num_devices);
for(unsigned i = 0; i < num_devices; ++i) {
binary_lengths[i] = binary_size;
binaries[i] = binary;
}

cl_int status;
scoped_array<cl_int> binary_status(num_devices);

cl_program program = clCreateProgramWithBinary(context, num_devices, devices, binary_lengths,
(const unsigned char **) binaries.get(), binary_status, &status);
checkError(status, "Failed to create program with binary");
for(unsigned i = 0; i < num_devices; ++i) {
checkError(binary_status[i], "Failed to load binary for device");
}

return program;
}


void initOpenCLPlatform_1()
{
cl_int err = CL_SUCCESS;


err = clGetPlatformIDs(0, NULL, &num_platforms);
if (CL_SUCCESS != err) {
printf("Error in clGetPlatformIDs %d\n", err);
exit(-1);
}
if (0 == num_platforms) {
printf("No OpenCL platforms found\n");
exit(-1);
}


std::vector<cl_platform_id> platform(num_platforms);


err = clGetPlatformIDs(num_platforms, &platform[0], 0);
if (CL_SUCCESS != err) {
printf("Error in clGetPlatformIDs %d\n", err);
exit(-1);
}


for (cl_int i = 0; i < num_platforms; i++) {
size_t length = 0;


err = clGetPlatformInfo(platform[i], CL_PLATFORM_NAME, 0, NULL, &length);
if (CL_SUCCESS != err) {
printf("Error in clGetPlatformInfo %d\n", err);
exit(-1);
}


std::vector<char> platform_name(length);
err = clGetPlatformInfo(platform[i], CL_PLATFORM_NAME, length, &platform_name[0], NULL);
if (CL_SUCCESS != err) {
printf("Error in clGetPlatformInfo %d\n", err);
exit(-1);
}


//if (strstr(&platform_name[0], "Altera")) {
if (strstr(&platform_name[0], "Intel")) {


err = clGetDeviceIDs(platform[i], CL_DEVICE_TYPE_ALL, 0, NULL, &numDevices);
if (CL_SUCCESS != err) {
printf("Error in clGetDeviceIDs %d\n", err);
exit(-1);
}


if (numDevices == 0) {
printf("No suitable devices found\n");
exit(-1);
}


cl_context_properties contextProperties[] = { CL_CONTEXT_PLATFORM, (cl_context_properties)platform[i], 0 };


context = clCreateContextFromType(contextProperties, CL_DEVICE_TYPE_ALL, NULL, NULL, &err);
if ((CL_SUCCESS != err) || (NULL == context)) {
printf("Error in clCreateContextFromType %d\n", err);
exit(-1);
}




err = clGetContextInfo(context, CL_CONTEXT_DEVICES, 2*sizeof(cl_device_id), deviceId, 0);
if (CL_SUCCESS != err) {
printf("Error in clGetContextInfo %d\n", err);
exit(-1);
}


const cl_command_queue_properties properties[] = { CL_QUEUE_PROPERTIES, CL_QUEUE_PROFILING_ENABLE, 0 };
commandQueue[0] = clCreateCommandQueueWithProperties(context, deviceId[DEVICE_ID_0], properties, &err);
if ((CL_SUCCESS != err) || (NULL == commandQueue[0])) {
printf("Error in clCreateCommandQueue %d\n", err);
exit(-1);
}
commandQueue[1] = clCreateCommandQueueWithProperties(context, deviceId[DEVICE_ID_1], properties, &err);
if ((CL_SUCCESS != err) || (NULL == commandQueue[1])) {
printf("Error in clCreateCommandQueue %d\n", err);
exit(-1);
}





std::string binary_file = getBoardBinaryFile("openclExample_1", deviceId[DEVICE_ID_0]);
printf("Using AOCX: %s\n", binary_file.c_str());
program[0] = createProgramFromBinary(context, binary_file.c_str(), &deviceId[DEVICE_ID_0], 1);


binary_file = getBoardBinaryFile("openclExample_2", deviceId[DEVICE_ID_1]);
printf("Using AOCX: %s\n", binary_file.c_str());
program[1] = createProgramFromBinary(context, binary_file.c_str(), &deviceId[DEVICE_ID_1], 1);
platform_init = 1;
}
}
}

void kernelLaunch()
{
initOpenCLPlatform_1();
/*kernel object creation for 1st kernel*/
kernel[0] = clCreateKernel(program[0], "examaple_kernel_1", &err);
if ((CL_SUCCESS != err) || (kernel[0] == NULL)) {
printf("Error in creating kernel[0] %d\n", err);
exit(-1);
}

//assigning kernel arguments for 1st kernel
...
//1st kernel launch
...
//copying back the output
...

/*kernel object creation for 2nd kernel*/
kernel[1] = clCreateKernel(program[1], "examaple_kernel_2", &err);
if ((CL_SUCCESS != err) || (kernel[1] == NULL)) {
printf("Error in creating kernel[1] %d\n", err);
exit(-1);
}

//assigning kernel arguments for 2nd kernel
...
err = clEnqueueTask(commandQueue[1], kernel[1], 0, NULL, NULL);
if (CL_SUCCESS != err) {
printf("Error in clEnqueueTask1 %d\n", err);
exit(-1);
}
}

int main()
{
kernelLaunch();
}

Peculiar Problem with Quartus 17.0 lite

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I am facing a peculiar problem while synthesizing with Quartus 17.0 lite for MAX 10 FPGA.

I was just trying to interface FPGA to LTC2400 ADC in free running mode. The program basically receives serial data and
extracts 14 bits from the parallel data stream. Everything works fine with the following statement
ADC_DAT <= {2'b0,ADC_TEMP[27:14]}-16'd1;

When I change the above code to

ADC_DAT <= {2'b0,ADC_TEMP[27:14]}-16'd100;

The data that I see through In system sources and probes editor is very random. Data continuously varies. When I do change back to my orginal
statement, things works fine. Any clues?

P.S: I will not be able to share the source code.

A2 sd card partition

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Does anyone know how to create a2 partition on sd card fwom Wondows? I did it on linux, but my teacher wants to do it on windows, i dont know for what.
Anyone solved it?

OpenCL based Convolutional Neural Network template

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Hello,

Is anyone aware of OpenCL based CNN implementation on Altera FPGAs?

I have looked into Intel Deep Learning Inference accelerator (https://software.intel.com/en-us/inf...ngine-devguide). It converts models generated by tensorflow and caffe into Intermediate representation. Anyone aware of converting custom graphs in caffe and tensorflow into FPGA binary format (.aocx)?

Regards,
Manoj.

Inout pin Warning

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Hi,

I am using Quartus version 17.1. I am receiving this warning message:

Warning (12620): Input port OE of I/O output buffer "fx3_dq[1]~output" is not connected, but the atom is driving a bi-directional pin

from Quartus while compiling. fx3_dq is 8 bits wide and is an inout wire connected from another module to the top level.
Why am I receiving this message?

I found this page : https://www.altera.com/support/suppo...62015_264.html
but it says this only occurs in version 14.1 and earlier. I also created tried changing the output by assigning it to high if an output enable signal is high and low if low, but I still receive this message.

-Thank you

Handling generic parameters in Quartus II 16.1 VHDL

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Hello to everyone,
I fpga and vhdl begginer and I am currently working on university project which concerns some array calculations on Cyclone V fpga and VHDL and I have a problem.

All custom made types are defined in package and also array dimensions are defined there too and this package is included in all .vhd files because these custom types are used as ports for some entities.
The problem starts when I try to extract array dimensions out of package, as generic for top-level entity.

I have found here some previous posts that I have modified into this:
type myArray is array(natural range <>) of std_logic_vector;
but this still does not work and later during instantiation of an component, quartus reports an error that unconstrained arrays are not allowed so it won't connect all necessary components.

Can anyone help me to achieve all things related to generic parameters and how to avoid this problem?

Regards,
Al

Cyclone 10LP PCI clamp diode before configuration complete

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Hello,
I've searched through the Cyclone 10 LP documentation and the forum and can't find out what the enable/disable state of the PCI clamp diodes is after power up and before configuration is complete.

Are the PCI clamp diodes enabled on device power up before FPGA configuration is complete?

Thanks, Chris

Documentation for non-latest Intel FPGA SDK for OpenCL

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Hello,

I recently got a Nallatech board whose BSP was created with tools v.17.1.
Therefore I plan to use same SDK version and review the corresponding documentation.
However, the documentation I could find online on the Intel/Altera websites corresponds to the latest one (18.0):

* https://www.altera.com/products/desi...l/support.html
* http://dl.altera.com/opencl/17.1/?ed...d_manager=dlm3

I was wondering if someone knows a page where I can find all documentation related specifically to the v.17.1.

Thanks!

Leo

Where can I get the package trace lengths for Cyclne IV GX ?

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