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Need helpl with DMA

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Hi everyone, i need help with using DMA in bare-metal project.

I have GHRD, and i need to transfer data (it just 0 to 127 count) from HPS RAM(as i understand from ftp://ftp.altera.com/up/pub/Intel_Ma..._from_FPGA.pdf , its address 0xffff0000) to FPGA OCRAM(its address 0xc0000000 in my system) using HPS DMA and then i show this data from FPGA OCRAM on LEDS(0xFF210040).

But something goes wrong, and when i show data on leds, i see only 0-3 ,but it must be 0-1-2-3-4-..127. And leds are blinks(i see 0-0-1-0-2-0-3), so i think it is zeros between 0 and 1, 1 and 2, 2 and 3,...
When i show on leds data direct from hps ram after initializing it, leds dont blink(i see 0-1-2-3-...-127)

I really dont understand why that happens and i spend 3 days , but i still dont know what i do wrong.

Please someone, help me to understand and fix it.



firstly, i setup dma:
Code:

ALT_STATUS_CODE socfpga_dma_setup(){
    printf("INFO: Setup DMA System ...\n");


    ALT_STATUS_CODE status = ALT_E_SUCCESS;


    if (status == ALT_E_SUCCESS)
    {
        // Configure everything as defaults.


        ALT_DMA_CFG_t dma_config;
        dma_config.manager_sec = ALT_DMA_SECURITY_DEFAULT;
        for (int i = 0; i < 8; ++i)
        {
            dma_config.irq_sec[i] = ALT_DMA_SECURITY_DEFAULT;
        }
        for (int i = 0; i < 32; ++i)
        {
            dma_config.periph_sec[i] = ALT_DMA_SECURITY_DEFAULT;
        }
        for (int i = 0; i < 4; ++i)
        {
            dma_config.periph_mux[i] = ALT_DMA_PERIPH_MUX_DEFAULT;
        }


        status = alt_dma_init(&dma_config);
        if (status != ALT_E_SUCCESS)
        {
            printf("ERROR: alt_dma_init() failed.\n");
        }
    }


    // Allocate the DMA channel


    if (status == ALT_E_SUCCESS)
    {
        status = alt_dma_channel_alloc_any(&channel);
        if (status != ALT_E_SUCCESS)
        {
            printf("ERROR: alt_dma_channel_alloc_any() failed.\n");
        }
        else
        {
            printf("INFO: Channel %d allocated.\n", (int)(channel));
        }
    }


    // Verify channel state


    if (status == ALT_E_SUCCESS)
    {
        ALT_DMA_CHANNEL_STATE_t state;
        status = alt_dma_channel_state_get(channel, &state);
        if (status == ALT_E_SUCCESS)
        {
            if (state != ALT_DMA_CHANNEL_STATE_STOPPED)
            {
                printf("ERROR: Bad initial channel state.\n");
                status = ALT_E_ERROR;
            }
        }
    }






    if (status == ALT_E_SUCCESS)
    {
        status = alt_dma_program_init(&program);
        if (status != ALT_E_SUCCESS)
        {
            printf("ERROR: alt_dma_program_init() failed.\n");
        }
        else
        {
            printf("INFO: Dma program_byffer initialized.\n");
        }
    }




    if (status == ALT_E_SUCCESS)
    {
        printf("INFO: Setup of DMA successful.\n\n");
    }
    else
    {
        printf("ERROR: Setup of DMA return non-SUCCESS %d.\n\n", (int)status);
    }


    return status;
}


then goes my main fuction:
Code:

ALT_STATUS_CODE dma_hpsram_to_fpgaram(){
    // Just base addresses of GHRD components
    const uint32_t ALT_LWFPGA_BASE        = 0xFF200000;
    const uint32_t ALT_LWFPGA_LED_OFFSET  = 0x00010040;


    const uint32_t ALT_H2F_BASE                = 0xc0000000;
    const uint32_t ALT_H2F_OCRAM_OFFSET      = 0x00000000;
    const uint32_t ALT_HPS_OCRAM              = 0xffff0000;


    // turn off leds
    alt_write_word(ALT_LWFPGA_BASE + ALT_LWFPGA_LED_OFFSET, 0);


    uint32_t temp=0;
    uint32_t offset=0;


    // write 0-127 to hps ram
    for (uint32_t i = 0; i < 128; ++i)
    {
        alt_write_byte(ALT_HPS_OCRAM+offset,temp);
        temp++;
        offset=offset+1;
    }


    // transfer data from hps ram to fpga ocram
    size_t size=128;
    uint32_t dst=ALT_H2F_BASE+ALT_H2F_OCRAM_OFFSET;
    uint32_t src=ALT_HPS_OCRAM;
    // this function i take from altera design examples (hps dma)
    dma_memory_to_memory(&src, &dst, size);


    // check result of transfer, looking at fpga ocram contents
    offset=0;
        for (uint32_t i = 0; i < 12800000; ++i)
        {
            if(i%100000==0)
            {
                // that big numbers for making leds switch less often
                alt_write_byte(ALT_LWFPGA_BASE+ALT_LWFPGA_LED_OFFSET, alt_read_byte(dst+offset));
                offset=offset+1;
            }
    }
    return ALT_E_SUCCESS;
}


it uses function from altera design examples( hps ram):
Code:

ALT_STATUS_CODE dma_memory_to_memory(void * src, void * dst, uint32_t size)
{
    ALT_STATUS_CODE status = ALT_E_SUCCESS;


    printf("INFO: Demo DMA memory to memory transfer.\n");


    // Copy source buffer over destination buffer
    if(status == ALT_E_SUCCESS)
    {
        status = alt_dma_memory_to_memory(channel, &program, dst, src, size, false, (ALT_DMA_EVENT_t)0);
    }


    // Wait for transfer to complete
    if (status == ALT_E_SUCCESS)
    {
        printf("INFO: Waiting for DMA transfer to complete.\n");
        ALT_DMA_CHANNEL_STATE_t channel_state = ALT_DMA_CHANNEL_STATE_EXECUTING;
        while((status == ALT_E_SUCCESS) && (channel_state != ALT_DMA_CHANNEL_STATE_STOPPED))
        {
            status = alt_dma_channel_state_get(channel, &channel_state);
            if(channel_state == ALT_DMA_CHANNEL_STATE_FAULTING)
            {
                ALT_DMA_CHANNEL_FAULT_t fault;
                alt_dma_channel_fault_status_get(channel, &fault);
                printf("ERROR: DMA CHannel Fault: %d\n", (int)fault);
                status = ALT_E_ERROR;
            }
        }
    }
    return status;
}


Some questions about intel HLS RTL design.

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Hello.


I am currently testing RTL design using Intel HLS. There are a number of errors that occur during HLS compilation and RTL conversion, but the error seems to lack work around or guide.
I'd like to ask you a few questions about this difficulty. This includes questions about HLS optimization errors and their own concepts.


- Is the intel HLS software for creating one independent RTL IP?
- Does a verilog top design with multiple sub-modules(instances) need to be designed manually? (I don't need to use SOPC or SOC. So, I also don't consider Qsys to design)
- Is it possible to obtain a generic sequential RTL design with HLS that does not include an Avalon interface? What is the exact purpose of the hls_always_run_component?
- The user manual says that the HLS/matrix_mult.h library for matrix multiplication is provided, but where is it located? Not found in Quaruts 17.1 standard and lite in use.
- Where can I find the meaning of error messages generated when converting the FPGA?
I got an error : Call parameter type does not match function signature! What does this mean?
Here's a code structure I've created. Please give me a lot of advice.

code: main.cpp

float (*function1(x,x,x))[3] {}
float (*function2(x,x,x))[3] {}
float (*function3(x,x,x))[3] {}

component float (*aaa())[2] {
float (*y1)[3] = function1(x,x,x);
float (*y2)[3] = function1(y1,x,x);
....
return y9;

int main() {
float (*aaa_out)[2] = aaa();
printf("%f\n", aaa_out[0][0]);
...
return 0;
}

Matrix multiplication design example

Factory pin state value

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When i buy Altera FPGA (Cyclone V GX for example), solder it on board, and give right voltage to power pin, wich state of user I/O pin i must see ? I think Tri-stated? Can somebody show me official documentation where i can see this information?

State Machine: Fitter seems to have problems with many states

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Good day,

is there are recommendation for state machines with a bigger number of states? Seems to me that the fitter does seem to need dramatically more compile time for state machines above 27 states. (Attached Project. State machine in module ram_ip_control).
What I already tried:
- Turn Fitter Initial Place Seed to 8
- Enabled Register duplication.

Analysis and synthesis clearly recognized the state machine.
The design uses only 12% of LEs of Cyclone V, one pll, one hard ram controller and one dual port ram synthesized as ram and not as LE. I tried to set all nessesary timing constraints.
However fitter runs on 75 % CPU Usage for a long time and stays at 36 % completion.
Is there anything that I can do, to solve this issue.

Edit: Using Quartus Prime Version 17.1.0 Build 590 and device is 5CGXFC5C6F27C7.
Greetings

Running 2 different kernels on 2 different devices in Emulator mode.

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Hi,
I'm trying to configure 2 different kernels on 2 different devices in emulator mode. But not able to configure on 2nd device.
I could able to launch kernel1 on device1 properly. When I'm trying to launch 2nd kernel on 2nd device then it is throwing "Error in clEnqueueTask1 45" error.
Error no 45 = CL_INVALID_PROGRAM_EXECUTABLE.


Tried with the following code:


#define DEVICE_ID_1 1
#define DEVICE_ID_0 0

cl_program createProgramFromBinary(cl_context context, const char *binary_file_name, const cl_device_id *devices, unsigned num_devices)
{
// Early exit for potentially the most common way to fail: AOCX does not exist.
if(!fileExists(binary_file_name)) {
printf("AOCX file '%s' does not exist.\n", binary_file_name);
checkError(CL_INVALID_PROGRAM, "Failed to load binary file");
}

// Load the binary.
size_t binary_size;
scoped_array<unsigned char> binary(loadBinaryFile(binary_file_name, &binary_size));
if(binary == NULL) {
checkError(CL_INVALID_PROGRAM, "Failed to load binary file");
}

scoped_array<size_t> binary_lengths(num_devices);
scoped_array<unsigned char *> binaries(num_devices);
for(unsigned i = 0; i < num_devices; ++i) {
binary_lengths[i] = binary_size;
binaries[i] = binary;
}

cl_int status;
scoped_array<cl_int> binary_status(num_devices);

cl_program program = clCreateProgramWithBinary(context, num_devices, devices, binary_lengths,
(const unsigned char **) binaries.get(), binary_status, &status);
checkError(status, "Failed to create program with binary");
for(unsigned i = 0; i < num_devices; ++i) {
checkError(binary_status[i], "Failed to load binary for device");
}

return program;
}


void initOpenCLPlatform_1()
{
cl_int err = CL_SUCCESS;


err = clGetPlatformIDs(0, NULL, &num_platforms);
if (CL_SUCCESS != err) {
printf("Error in clGetPlatformIDs %d\n", err);
exit(-1);
}
if (0 == num_platforms) {
printf("No OpenCL platforms found\n");
exit(-1);
}


std::vector<cl_platform_id> platform(num_platforms);


err = clGetPlatformIDs(num_platforms, &platform[0], 0);
if (CL_SUCCESS != err) {
printf("Error in clGetPlatformIDs %d\n", err);
exit(-1);
}


for (cl_int i = 0; i < num_platforms; i++) {
size_t length = 0;


err = clGetPlatformInfo(platform[i], CL_PLATFORM_NAME, 0, NULL, &length);
if (CL_SUCCESS != err) {
printf("Error in clGetPlatformInfo %d\n", err);
exit(-1);
}


std::vector<char> platform_name(length);
err = clGetPlatformInfo(platform[i], CL_PLATFORM_NAME, length, &platform_name[0], NULL);
if (CL_SUCCESS != err) {
printf("Error in clGetPlatformInfo %d\n", err);
exit(-1);
}


//if (strstr(&platform_name[0], "Altera")) {
if (strstr(&platform_name[0], "Intel")) {


err = clGetDeviceIDs(platform[i], CL_DEVICE_TYPE_ALL, 0, NULL, &numDevices);
if (CL_SUCCESS != err) {
printf("Error in clGetDeviceIDs %d\n", err);
exit(-1);
}


if (numDevices == 0) {
printf("No suitable devices found\n");
exit(-1);
}


cl_context_properties contextProperties[] = { CL_CONTEXT_PLATFORM, (cl_context_properties)platform[i], 0 };


context = clCreateContextFromType(contextProperties, CL_DEVICE_TYPE_ALL, NULL, NULL, &err);
if ((CL_SUCCESS != err) || (NULL == context)) {
printf("Error in clCreateContextFromType %d\n", err);
exit(-1);
}




err = clGetContextInfo(context, CL_CONTEXT_DEVICES, 2*sizeof(cl_device_id), deviceId, 0);
if (CL_SUCCESS != err) {
printf("Error in clGetContextInfo %d\n", err);
exit(-1);
}


const cl_command_queue_properties properties[] = { CL_QUEUE_PROPERTIES, CL_QUEUE_PROFILING_ENABLE, 0 };
commandQueue[0] = clCreateCommandQueueWithProperties(context, deviceId[DEVICE_ID_0], properties, &err);
if ((CL_SUCCESS != err) || (NULL == commandQueue[0])) {
printf("Error in clCreateCommandQueue %d\n", err);
exit(-1);
}
commandQueue[1] = clCreateCommandQueueWithProperties(context, deviceId[DEVICE_ID_1], properties, &err);
if ((CL_SUCCESS != err) || (NULL == commandQueue[1])) {
printf("Error in clCreateCommandQueue %d\n", err);
exit(-1);
}





std::string binary_file = getBoardBinaryFile("openclExample_1", deviceId[DEVICE_ID_0]);
printf("Using AOCX: %s\n", binary_file.c_str());
program[0] = createProgramFromBinary(context, binary_file.c_str(), &deviceId[DEVICE_ID_0], 1);


binary_file = getBoardBinaryFile("openclExample_2", deviceId[DEVICE_ID_1]);
printf("Using AOCX: %s\n", binary_file.c_str());
program[1] = createProgramFromBinary(context, binary_file.c_str(), &deviceId[DEVICE_ID_1], 1);
platform_init = 1;
}
}
}

void kernelLaunch()
{
initOpenCLPlatform_1();
/*kernel object creation for 1st kernel*/
kernel[0] = clCreateKernel(program[0], "examaple_kernel_1", &err);
if ((CL_SUCCESS != err) || (kernel[0] == NULL)) {
printf("Error in creating kernel[0] %d\n", err);
exit(-1);
}

//assigning kernel arguments for 1st kernel
...
//1st kernel launch
...
//copying back the output
...

/*kernel object creation for 2nd kernel*/
kernel[1] = clCreateKernel(program[1], "examaple_kernel_2", &err);
if ((CL_SUCCESS != err) || (kernel[1] == NULL)) {
printf("Error in creating kernel[1] %d\n", err);
exit(-1);
}

//assigning kernel arguments for 2nd kernel
...
err = clEnqueueTask(commandQueue[1], kernel[1], 0, NULL, NULL);
if (CL_SUCCESS != err) {
printf("Error in clEnqueueTask1 %d\n", err);
exit(-1);
}
}

int main()
{
kernelLaunch();
}

Peculiar Problem with Quartus 17.0 lite

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I am facing a peculiar problem while synthesizing with Quartus 17.0 lite for MAX 10 FPGA.

I was just trying to interface FPGA to LTC2400 ADC in free running mode. The program basically receives serial data and
extracts 14 bits from the parallel data stream. Everything works fine with the following statement
ADC_DAT <= {2'b0,ADC_TEMP[27:14]}-16'd1;

When I change the above code to

ADC_DAT <= {2'b0,ADC_TEMP[27:14]}-16'd100;

The data that I see through In system sources and probes editor is very random. Data continuously varies. When I do change back to my orginal
statement, things works fine. Any clues?

P.S: I will not be able to share the source code.

A2 sd card partition

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Does anyone know how to create a2 partition on sd card fwom Wondows? I did it on linux, but my teacher wants to do it on windows, i dont know for what.
Anyone solved it?

OpenCL based Convolutional Neural Network template

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Hello,

Is anyone aware of OpenCL based CNN implementation on Altera FPGAs?

I have looked into Intel Deep Learning Inference accelerator (https://software.intel.com/en-us/inf...ngine-devguide). It converts models generated by tensorflow and caffe into Intermediate representation. Anyone aware of converting custom graphs in caffe and tensorflow into FPGA binary format (.aocx)?

Regards,
Manoj.

Inout pin Warning

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Hi,

I am using Quartus version 17.1. I am receiving this warning message:

Warning (12620): Input port OE of I/O output buffer "fx3_dq[1]~output" is not connected, but the atom is driving a bi-directional pin

from Quartus while compiling. fx3_dq is 8 bits wide and is an inout wire connected from another module to the top level.
Why am I receiving this message?

I found this page : https://www.altera.com/support/suppo...62015_264.html
but it says this only occurs in version 14.1 and earlier. I also created tried changing the output by assigning it to high if an output enable signal is high and low if low, but I still receive this message.

-Thank you

Handling generic parameters in Quartus II 16.1 VHDL

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Hello to everyone,
I fpga and vhdl begginer and I am currently working on university project which concerns some array calculations on Cyclone V fpga and VHDL and I have a problem.

All custom made types are defined in package and also array dimensions are defined there too and this package is included in all .vhd files because these custom types are used as ports for some entities.
The problem starts when I try to extract array dimensions out of package, as generic for top-level entity.

I have found here some previous posts that I have modified into this:
type myArray is array(natural range <>) of std_logic_vector;
but this still does not work and later during instantiation of an component, quartus reports an error that unconstrained arrays are not allowed so it won't connect all necessary components.

Can anyone help me to achieve all things related to generic parameters and how to avoid this problem?

Regards,
Al

Cyclone 10LP PCI clamp diode before configuration complete

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Hello,
I've searched through the Cyclone 10 LP documentation and the forum and can't find out what the enable/disable state of the PCI clamp diodes is after power up and before configuration is complete.

Are the PCI clamp diodes enabled on device power up before FPGA configuration is complete?

Thanks, Chris

Documentation for non-latest Intel FPGA SDK for OpenCL

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Hello,

I recently got a Nallatech board whose BSP was created with tools v.17.1.
Therefore I plan to use same SDK version and review the corresponding documentation.
However, the documentation I could find online on the Intel/Altera websites corresponds to the latest one (18.0):

* https://www.altera.com/products/desi...l/support.html
* http://dl.altera.com/opencl/17.1/?ed...d_manager=dlm3

I was wondering if someone knows a page where I can find all documentation related specifically to the v.17.1.

Thanks!

Leo

I need help about quartus

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Hi falles, I am writing you from Turkiye
I have to make a quartus project
maybe it is very simple but I dont know anything about quartus and FPGA
I need to design a 3 bits multiplier in quartus
I am posting the circuit on paper
how can I design it in quartus
if there is someone in the forum who knows about it, pls help me
thank you
have a nice days guys

Attached Images

Hard Ip Core and power

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Good afternoon, colleagues.


I have Stratix V, I have been trying for a long time to run hard ip core pcie (Constantly get lsmsm = 0000).

Today I decided to measure the tension on the pins. And I found out that in 2 out of 6 pins VCCHSSI_L (Transceiver PCS power supply (left side)) there is no voltage. How do you think, can this be the reason for the launch problem?

Issues with changing to a larger memory CPLD

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I have project that I was using 5M570ZT144C5N. I was running out of logic elements and I had to change to 5M1270ZT144C5N. I recompiled with the new CPLD selected and deployed to the target without an issue. However, the project now is using the 5M1270ZT144C5N and does not behave the same when using the 5M570ZT144C5N. What do I need to do to fix this?

Thank You

Missing NIOS II Hardware in run configurations

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Folks,
I have inherited a mature design from a previous project. The target is a DE0_nano, with a NIOS II/f processor in the design. My qts version is 11.1, fully licensed, windows 10 env. The project builds without error. When I launch eclipse, it builds the BSP and the processor application code. What is missing is a NIOS II hardware target when I bring up the run or debug configurations dialog. I cant load and run the project on the Nios using eclipse.

I have built everything from scratch, rebuilt the BSP and this selection is not in my configuration. A developer using the exact same project directory with the exact tools can bring eclipse up and the NIOS II Hardware is available. I can program the FPGA OK, and download and run the NIOS using the command line, so I kno that the JTAG chain is intact and working.

Question: How does eclipse kno that a NIOS II is "out there" as a viable target to load and debug?

Thanks,
Ed

FPGA Cyclone V

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Hello,
Actually, I have a project with an FPGA, I installed Quartus II 12.1 Subscription Edition without license from the original CD.
I try to do my simple application and everything was good until the compilation was successful, but when I connect my board with a USB - blaster. I try to charge the file" .sof " I don't find it. What's the problem?
Is it related to license or something like that?
My board is cyclone V ref:5CSEMA5F31C6N and I choose 5CSEMA5F31C6 in QuartusII
Is there a deiiference in the device?
Please help me, I need to start my project
There are some attachments to show u more details.
Thanks.
Attached Images

Critical Path in Loop

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I'm trying to the use the details of the loop analysis report to decrease the ii of a loop. Unfortunately I can't find a good explanation about some of the details. I've posted the output of part of the report below, followed by some questions.
Code:

The critical path that prevented successful II = 1 scheduling:

Question 1) - The first bullet says the number of nodes in critical path is beyond what the compiler captured, and the top 13 FAILING does are listed. Some of the bullets below that are > 1 clock cycle, some are < 1 clock cycle. Is each bullet an independent critical path? If so, aren't the paths < 1 NOT failing? Am I missing something here? If I know I can focus on the bullets that are > 1 to get to an ii of 1 it would be easier.

Question 2) - Bullet 1 indicates a 1.1 clock cycle select operation on the "stallRead" variable. I can't fathom how this logic can't be accomplished in a single clock cycle. See the code segment below. I want to read from a channel on every loop, until an end of frame flag is set in the read data. At that point, stall for 6 clock cycles then then start reading again.

Code:

uchar stallRead = 0;       
while(1)
    {       
        if (stallRead == 0)
        {                   
            rxData      = read_channel_intel(TOCLIENT);
            rxWord[0]  = rxData.data;           
            rxStatus[0] = parseStatus(rxData.header);
            if (rxStatus[0].eop) //if we hit a end of frame flag, stall for a few clock cycles
                stallRead = 0x40;
        }
        else
            stallMacRead = stallMacRead >> 1;


                case statement and other logic......

Thanks, any suggestions or pointing to examples or documentation is appreciated.

Factory pin state value

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When i buy Altera FPGA (Cyclone V GX for example), solder it on board, and give right voltage to power pin, wich state of user I/O pin i must see ? I think Tri-stated? Can somebody show me official documentation where i can see this information?
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