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State Machine: Fitter seems to have problems with many states

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Good day,

is there are recommendation for state machines with a bigger number of states? Seems to me that the fitter does seem to need dramatically more compile time for state machines above 27 states. (Attached Project. State machine in module ram_ip_control).
What I already tried:
- Turn Fitter Initial Place Seed to 8
- Enabled Register duplication.

Analysis and synthesis clearly recognized the state machine.
The design uses only 12% of LEs of Cyclone V, one pll, one hard ram controller and one dual port ram synthesized as ram and not as LE. I tried to set all nessesary timing constraints.
However fitter runs on 75 % CPU Usage for a long time and stays at 36 % completion.
Is there anything that I can do, to solve this issue.

Edit: Using Quartus Prime Version 17.1.0 Build 590 and device is 5CGXFC5C6F27C7.
Greetings

Running 2 different kernels on 2 different devices in Emulator mode.

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Hi,
I'm trying to configure 2 different kernels on 2 different devices in emulator mode. But not able to configure on 2nd device.
I could able to launch kernel1 on device1 properly. When I'm trying to launch 2nd kernel on 2nd device then it is throwing "Error in clEnqueueTask1 45" error.
Error no 45 = CL_INVALID_PROGRAM_EXECUTABLE.


Tried with the following code:


#define DEVICE_ID_1 1
#define DEVICE_ID_0 0

cl_program createProgramFromBinary(cl_context context, const char *binary_file_name, const cl_device_id *devices, unsigned num_devices)
{
// Early exit for potentially the most common way to fail: AOCX does not exist.
if(!fileExists(binary_file_name)) {
printf("AOCX file '%s' does not exist.\n", binary_file_name);
checkError(CL_INVALID_PROGRAM, "Failed to load binary file");
}

// Load the binary.
size_t binary_size;
scoped_array<unsigned char> binary(loadBinaryFile(binary_file_name, &binary_size));
if(binary == NULL) {
checkError(CL_INVALID_PROGRAM, "Failed to load binary file");
}

scoped_array<size_t> binary_lengths(num_devices);
scoped_array<unsigned char *> binaries(num_devices);
for(unsigned i = 0; i < num_devices; ++i) {
binary_lengths[i] = binary_size;
binaries[i] = binary;
}

cl_int status;
scoped_array<cl_int> binary_status(num_devices);

cl_program program = clCreateProgramWithBinary(context, num_devices, devices, binary_lengths,
(const unsigned char **) binaries.get(), binary_status, &status);
checkError(status, "Failed to create program with binary");
for(unsigned i = 0; i < num_devices; ++i) {
checkError(binary_status[i], "Failed to load binary for device");
}

return program;
}


void initOpenCLPlatform_1()
{
cl_int err = CL_SUCCESS;


err = clGetPlatformIDs(0, NULL, &num_platforms);
if (CL_SUCCESS != err) {
printf("Error in clGetPlatformIDs %d\n", err);
exit(-1);
}
if (0 == num_platforms) {
printf("No OpenCL platforms found\n");
exit(-1);
}


std::vector<cl_platform_id> platform(num_platforms);


err = clGetPlatformIDs(num_platforms, &platform[0], 0);
if (CL_SUCCESS != err) {
printf("Error in clGetPlatformIDs %d\n", err);
exit(-1);
}


for (cl_int i = 0; i < num_platforms; i++) {
size_t length = 0;


err = clGetPlatformInfo(platform[i], CL_PLATFORM_NAME, 0, NULL, &length);
if (CL_SUCCESS != err) {
printf("Error in clGetPlatformInfo %d\n", err);
exit(-1);
}


std::vector<char> platform_name(length);
err = clGetPlatformInfo(platform[i], CL_PLATFORM_NAME, length, &platform_name[0], NULL);
if (CL_SUCCESS != err) {
printf("Error in clGetPlatformInfo %d\n", err);
exit(-1);
}


//if (strstr(&platform_name[0], "Altera")) {
if (strstr(&platform_name[0], "Intel")) {


err = clGetDeviceIDs(platform[i], CL_DEVICE_TYPE_ALL, 0, NULL, &numDevices);
if (CL_SUCCESS != err) {
printf("Error in clGetDeviceIDs %d\n", err);
exit(-1);
}


if (numDevices == 0) {
printf("No suitable devices found\n");
exit(-1);
}


cl_context_properties contextProperties[] = { CL_CONTEXT_PLATFORM, (cl_context_properties)platform[i], 0 };


context = clCreateContextFromType(contextProperties, CL_DEVICE_TYPE_ALL, NULL, NULL, &err);
if ((CL_SUCCESS != err) || (NULL == context)) {
printf("Error in clCreateContextFromType %d\n", err);
exit(-1);
}




err = clGetContextInfo(context, CL_CONTEXT_DEVICES, 2*sizeof(cl_device_id), deviceId, 0);
if (CL_SUCCESS != err) {
printf("Error in clGetContextInfo %d\n", err);
exit(-1);
}


const cl_command_queue_properties properties[] = { CL_QUEUE_PROPERTIES, CL_QUEUE_PROFILING_ENABLE, 0 };
commandQueue[0] = clCreateCommandQueueWithProperties(context, deviceId[DEVICE_ID_0], properties, &err);
if ((CL_SUCCESS != err) || (NULL == commandQueue[0])) {
printf("Error in clCreateCommandQueue %d\n", err);
exit(-1);
}
commandQueue[1] = clCreateCommandQueueWithProperties(context, deviceId[DEVICE_ID_1], properties, &err);
if ((CL_SUCCESS != err) || (NULL == commandQueue[1])) {
printf("Error in clCreateCommandQueue %d\n", err);
exit(-1);
}





std::string binary_file = getBoardBinaryFile("openclExample_1", deviceId[DEVICE_ID_0]);
printf("Using AOCX: %s\n", binary_file.c_str());
program[0] = createProgramFromBinary(context, binary_file.c_str(), &deviceId[DEVICE_ID_0], 1);


binary_file = getBoardBinaryFile("openclExample_2", deviceId[DEVICE_ID_1]);
printf("Using AOCX: %s\n", binary_file.c_str());
program[1] = createProgramFromBinary(context, binary_file.c_str(), &deviceId[DEVICE_ID_1], 1);
platform_init = 1;
}
}
}

void kernelLaunch()
{
initOpenCLPlatform_1();
/*kernel object creation for 1st kernel*/
kernel[0] = clCreateKernel(program[0], "examaple_kernel_1", &err);
if ((CL_SUCCESS != err) || (kernel[0] == NULL)) {
printf("Error in creating kernel[0] %d\n", err);
exit(-1);
}

//assigning kernel arguments for 1st kernel
...
//1st kernel launch
...
//copying back the output
...

/*kernel object creation for 2nd kernel*/
kernel[1] = clCreateKernel(program[1], "examaple_kernel_2", &err);
if ((CL_SUCCESS != err) || (kernel[1] == NULL)) {
printf("Error in creating kernel[1] %d\n", err);
exit(-1);
}

//assigning kernel arguments for 2nd kernel
...
err = clEnqueueTask(commandQueue[1], kernel[1], 0, NULL, NULL);
if (CL_SUCCESS != err) {
printf("Error in clEnqueueTask1 %d\n", err);
exit(-1);
}
}

int main()
{
kernelLaunch();
}

Peculiar Problem with Quartus 17.0 lite

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I am facing a peculiar problem while synthesizing with Quartus 17.0 lite for MAX 10 FPGA.

I was just trying to interface FPGA to LTC2400 ADC in free running mode. The program basically receives serial data and
extracts 14 bits from the parallel data stream. Everything works fine with the following statement
ADC_DAT <= {2'b0,ADC_TEMP[27:14]}-16'd1;

When I change the above code to

ADC_DAT <= {2'b0,ADC_TEMP[27:14]}-16'd100;

The data that I see through In system sources and probes editor is very random. Data continuously varies. When I do change back to my orginal
statement, things works fine. Any clues?

P.S: I will not be able to share the source code.

A2 sd card partition

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Does anyone know how to create a2 partition on sd card fwom Wondows? I did it on linux, but my teacher wants to do it on windows, i dont know for what.
Anyone solved it?

OpenCL based Convolutional Neural Network template

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Hello,

Is anyone aware of OpenCL based CNN implementation on Altera FPGAs?

I have looked into Intel Deep Learning Inference accelerator (https://software.intel.com/en-us/inf...ngine-devguide). It converts models generated by tensorflow and caffe into Intermediate representation. Anyone aware of converting custom graphs in caffe and tensorflow into FPGA binary format (.aocx)?

Regards,
Manoj.

Inout pin Warning

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Hi,

I am using Quartus version 17.1. I am receiving this warning message:

Warning (12620): Input port OE of I/O output buffer "fx3_dq[1]~output" is not connected, but the atom is driving a bi-directional pin

from Quartus while compiling. fx3_dq is 8 bits wide and is an inout wire connected from another module to the top level.
Why am I receiving this message?

I found this page : https://www.altera.com/support/suppo...62015_264.html
but it says this only occurs in version 14.1 and earlier. I also created tried changing the output by assigning it to high if an output enable signal is high and low if low, but I still receive this message.

-Thank you

Handling generic parameters in Quartus II 16.1 VHDL

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Hello to everyone,
I fpga and vhdl begginer and I am currently working on university project which concerns some array calculations on Cyclone V fpga and VHDL and I have a problem.

All custom made types are defined in package and also array dimensions are defined there too and this package is included in all .vhd files because these custom types are used as ports for some entities.
The problem starts when I try to extract array dimensions out of package, as generic for top-level entity.

I have found here some previous posts that I have modified into this:
type myArray is array(natural range <>) of std_logic_vector;
but this still does not work and later during instantiation of an component, quartus reports an error that unconstrained arrays are not allowed so it won't connect all necessary components.

Can anyone help me to achieve all things related to generic parameters and how to avoid this problem?

Regards,
Al

Cyclone 10LP PCI clamp diode before configuration complete

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Hello,
I've searched through the Cyclone 10 LP documentation and the forum and can't find out what the enable/disable state of the PCI clamp diodes is after power up and before configuration is complete.

Are the PCI clamp diodes enabled on device power up before FPGA configuration is complete?

Thanks, Chris

Documentation for non-latest Intel FPGA SDK for OpenCL

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Hello,

I recently got a Nallatech board whose BSP was created with tools v.17.1.
Therefore I plan to use same SDK version and review the corresponding documentation.
However, the documentation I could find online on the Intel/Altera websites corresponds to the latest one (18.0):

* https://www.altera.com/products/desi...l/support.html
* http://dl.altera.com/opencl/17.1/?ed...d_manager=dlm3

I was wondering if someone knows a page where I can find all documentation related specifically to the v.17.1.

Thanks!

Leo

I need help about quartus

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Hi falles, I am writing you from Turkiye
I have to make a quartus project
maybe it is very simple but I dont know anything about quartus and FPGA
I need to design a 3 bits multiplier in quartus
I am posting the circuit on paper
how can I design it in quartus
if there is someone in the forum who knows about it, pls help me
thank you
have a nice days guys

Attached Images

Hard Ip Core and power

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Good afternoon, colleagues.


I have Stratix V, I have been trying for a long time to run hard ip core pcie (Constantly get lsmsm = 0000).

Today I decided to measure the tension on the pins. And I found out that in 2 out of 6 pins VCCHSSI_L (Transceiver PCS power supply (left side)) there is no voltage. How do you think, can this be the reason for the launch problem?

Issues with changing to a larger memory CPLD

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I have project that I was using 5M570ZT144C5N. I was running out of logic elements and I had to change to 5M1270ZT144C5N. I recompiled with the new CPLD selected and deployed to the target without an issue. However, the project now is using the 5M1270ZT144C5N and does not behave the same when using the 5M570ZT144C5N. What do I need to do to fix this?

Thank You

Missing NIOS II Hardware in run configurations

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Folks,
I have inherited a mature design from a previous project. The target is a DE0_nano, with a NIOS II/f processor in the design. My qts version is 11.1, fully licensed, windows 10 env. The project builds without error. When I launch eclipse, it builds the BSP and the processor application code. What is missing is a NIOS II hardware target when I bring up the run or debug configurations dialog. I cant load and run the project on the Nios using eclipse.

I have built everything from scratch, rebuilt the BSP and this selection is not in my configuration. A developer using the exact same project directory with the exact tools can bring eclipse up and the NIOS II Hardware is available. I can program the FPGA OK, and download and run the NIOS using the command line, so I kno that the JTAG chain is intact and working.

Question: How does eclipse kno that a NIOS II is "out there" as a viable target to load and debug?

Thanks,
Ed

FPGA Cyclone V

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Hello,
Actually, I have a project with an FPGA, I installed Quartus II 12.1 Subscription Edition without license from the original CD.
I try to do my simple application and everything was good until the compilation was successful, but when I connect my board with a USB - blaster. I try to charge the file" .sof " I don't find it. What's the problem?
Is it related to license or something like that?
My board is cyclone V ref:5CSEMA5F31C6N and I choose 5CSEMA5F31C6 in QuartusII
Is there a deiiference in the device?
Please help me, I need to start my project
There are some attachments to show u more details.
Thanks.
Attached Images

Critical Path in Loop

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I'm trying to the use the details of the loop analysis report to decrease the ii of a loop. Unfortunately I can't find a good explanation about some of the details. I've posted the output of part of the report below, followed by some questions.
Code:

The critical path that prevented successful II = 1 scheduling:

Question 1) - The first bullet says the number of nodes in critical path is beyond what the compiler captured, and the top 13 FAILING does are listed. Some of the bullets below that are > 1 clock cycle, some are < 1 clock cycle. Is each bullet an independent critical path? If so, aren't the paths < 1 NOT failing? Am I missing something here? If I know I can focus on the bullets that are > 1 to get to an ii of 1 it would be easier.

Question 2) - Bullet 1 indicates a 1.1 clock cycle select operation on the "stallRead" variable. I can't fathom how this logic can't be accomplished in a single clock cycle. See the code segment below. I want to read from a channel on every loop, until an end of frame flag is set in the read data. At that point, stall for 6 clock cycles then then start reading again.

Code:

uchar stallRead = 0;       
while(1)
    {       
        if (stallRead == 0)
        {                   
            rxData      = read_channel_intel(TOCLIENT);
            rxWord[0]  = rxData.data;           
            rxStatus[0] = parseStatus(rxData.header);
            if (rxStatus[0].eop) //if we hit a end of frame flag, stall for a few clock cycles
                stallRead = 0x40;
        }
        else
            stallMacRead = stallMacRead >> 1;


                case statement and other logic......

Thanks, any suggestions or pointing to examples or documentation is appreciated.

Does SignalTap work with other ICs in the JTAG chain?

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Does Quartus II SignalTap work with ICs in the JTAG chain other than the Altera FPGA where SignalTap is being utilized? I get "Invalid JTAG configuration" in the SignalTap II Logic Analyzer stp window.

NIOS with Configuration via Protocol (CvP) Design

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I am currently working to implement a NIOS on a CvP design on the Peripheral portion.

I've taken the .sof, which contains the peripheral and core portions of my CvP design and loaded it onto my Stratix 5.

I am running into issues when attempting to run my application, I get the error: No Nios II target connection paths were located. Check connections and that a Nios II .sof is downloaded.

After seeing this failure, I stripped down my project to just the NIOS II, and it runs a hello world application fine using the same clk and reset pins.

Does anyone have any idea on what could be going on?

Thanks.

Driving Ladder DAC

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Hi,

Im trying to drive a resistor ladder DAC from my DE-1 SOC board, despite of my DAC being very accurate im getting somewhat shotty results.
The setup is relatively simple driving the resistors directly from the board. Right now im using plain old 3.3v ttl to drive it.

I was wondering what output standard is best used, and if I can drive Z to it without any troubles?




Kind Regards,
Camper.

QuartusII 18.0 - number of processors used during compilation question

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Hi,
I'm wondering whether in Quartus II 18.0 parallel processor usage is (again) limited to full versions, i.e. not available in the lite (free) Edition.
Under Settings => Compilation Settings => Parallel compilaton moving the mouse pointer to either option in section parallel compilation it shows the hint "to use this feature you must purchase a full featured Edition of the Quartus Prime Software".
Starting the compilation, in the message window there is the message "Info (20032): Parallel compilation is enabled and will use up to 4 processors"
Contrary to this in the flow report, only use of one processor of my QuadCore is shown (in 17.1 all four were stated to be used).

Is therefore the info in the message window false and Intel PSG "advertises" v18.0 to reduce compilaton times and memory usage, but does not mention this benefits now require to spend $2,995 ? :confused:

Thus changing from 17.1 to 18.0 in free Edition is more a drawback in Performance.. :(

Kind regards, Carlhermann

What is VTAP10?

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Hi guys. So I have my Max 10 development kit installed and am checking to be sure I have the drivers installed properly.
Quartus Prime 17.1 is running fine. :cool:

But now I have what seems to be a problem.

The Intel Max10 Dev board runs the included board software OK, when it comes to using the programmer, I have questions.

I have been able to get a simple design to program and run, but only after fiddling with 'auto-detect', and removing a detected hardware called VTAP10.
There is no VTAP10 showing up in the tutorial demo I followed, but the tutorial was using 15.0.

I could use a little help.
What is VTAP10 and how does it fit into the picture?
Is the VTAP10 hardware part of the Altera/Intel Development board, or am I looking at a bad USB-blaster driver install or other mess up?
What documentation should I reference to understand this part better? Thanks for your help.
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