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Port property DRIVEN_BY and dummy output ports

May 8, 2018, 5:43 am
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My design has a number of modules with Avalon-ST sinks and sources. None of them use packets for communication. However, it is not possible to connect sources without packet support to, for example, SGDMA sinks. Instead of adding startofpacket and endofpacket ports to the HDL of each module, I tried adding the following lines to my _hw.tcl file:
Code:
set_port_property stream_eop DRIVEN_BY 0
set_port_property stream_sop DRIVEN_BY 0
However, Quartus is not happy with this, and the compilation ends with errors:
Code:
Error (12002): Port "stream_eop" does not exist in macrofunction "adc_pio_0"
Error (12002): Port "stream_sop" does not exist in macrofunction "adc_pio_0"
Is it really necessary to include the ports in HDL? If so, what is the use of the DRIVEN_BY port property?
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Upgrade Quartus 17.0 to Quartus 18.0 issue

May 9, 2018, 1:59 am
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Hi everyone,
I have a problem with Quartus 18.0 standard version.
If I compile my project on Quartus 17.0 it needs about 75 minutes, on the other hand after the upgrade to 18.0 standard version it needs 225 minutes, it's a huge difference.


The settings of the quartus 17.0 and 18.0 are the same, both FPGA codes works. However, I don't understand why.


Some advices?

Just tried to delete the database nothing's changed.
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Arria 10 TSE with GXB

May 9, 2018, 2:21 am
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Dear Sir,

I am working on a design on the DE5A-NET-DDR4. But it is not for 10G or 40G Ethernet.
It is a Gigabit Ethernet design. It is from our old project. It was working well on the
Arria 5 starter kit. It uses a TSE with LVDS design for the PCS and PMA. I am not
modify it onto the DE5 board, by modifying the PMA into GXB. In addition, the GXB needs
two additional clocks, tx_serial_clk and rx_cdr_refclk. I have used an fPLL to generate
a mcgb_serial_clk for the tx_serial_clk and a 125Mhz from input pin (it is from a clock
synthesizer si5340). The compilation is ok now. The PCS configuration is follow the
TSE manual to set as below.

0x13 = 0x13
0x12 = 0x12d0
0x00 = 0x5140
0x14 = 0x0000
0x00 = 0xd140

The attached jpg file is the verilog code for the tse connection check. I don't know why the
pcs loopback is not working.


Regards,


Peter Chang


Attached Images
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Need for Shelf life & Packing Type of the following MPN's.

May 9, 2018, 3:06 am
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0
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Hi,

This is Prachi from Flex.

We are currently working with one of our manufacturing plant to collect required Data.

Site: Zhuhai

Please help us to provide: -


· Packing type (If tray – please provide – whether Hard tray or Soft tray), & Shelf life

Hard Tray means “It is a plastic chip tray of conductive polystyrene and antistatic ABS. Customer will be satisfied quality, price and delivery of ADY products since our corporate factory in Taiwan control the total operation from mold design, mold assemble, production, inspection to packing by themselves”
&
Soft Tray means “It is a tray formed by vaccuming resin sheet. SOFT TRAY is designed and manufactured according to the part shape by the best size”


Kindly provide the datasheet for the same.

Customer Flex P/N Description MFR MPN Packing type Shelf life
Cisco CISH-16-100294-01 IC-FPGA,5AGXMA5D4-4.0,FCBGA,67 ALTERA 5AGXMA5D4F27C4N
Cisco CISH-16-100383-01 IC-FPGA,EP4CE40-8.0,FBGA,780 P ALTERA EP4CE40F29C8N
Cisco CISH-16-100521-01 IC-FPGA,5AGXMA7G4-5.0,FCBGA,89 ALTERA 5AGXMA7G4F31I5NAB
Cisco CISH-16-100818-01 IC-FPGA,5AGXFB3H4-5.0,FCBGA,11 ALTERA 5AGXFB3H4F35I5G
Cisco CISH-16-4323-01 IC,PLD-FPGA,EP4CGX22C-7,FBGA32 ALTERA EP4CGX22CF19I7N
Cisco CISH-16-4426-01 IC-FPGA,5AGTFD7K3-5.0,FCBGA,15 ALTERA 5AGTFD7K3F40I5NAC
Cisco CISH-16-4405-01 IC-FPGA,EP4CGX75D-7.0,FBGA,672 ALTERA EP4CGX75DF27C6N
Cisco CISH-16-4174-01 IC,PLD-FPGA,EP4CGX30C-8, FBGA4 ALTERA EP4CGX30CF23C8N
Cisco CISH-16-4243-01 IC,PLD-FPGA,EP4CGX50C-8,FBGA48 ALTERA EP4CGX50CF23C8N
Cisco CISH-16-101088-01 IC-FPGA,10AX032H4-3.0,FPBGA,11 ALTERA 10AX032H4F34E3SG


· Shelf life

Customer Flex P/N Description MFR MPN Shelf life
Cisco CISH-16-3281-02 IC-FPGA,EP2C20-8,FBGA256,PB-Fr ALTERA EP2C20F256C8N
Cisco CISH-16-4088-01 IC,PLD-FPGA,EP2AGX45CU17I3N,I- ALTERA EP2AGX45CU17I3G
Cisco CISH-16-3065-01 IC-FPGA,EP1C3-8,TQFP144 ALTERA EP1C3T144C8N

Please note that this is the critical project we are handling for Zhuhai site. Any delay in providing the data will affect in receiving the part.
Also there are possibilities of rejection in the shipment.
Hence we request you to provide the data as early as possible.

Let me know for any help.
Thank you.
↧

Is sGDMA integration correct in this SoC ??

May 9, 2018, 6:44 am
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Hello all,

I am using modular scatter-gather DMA core to transfer data from my custom IP: custom_design_32_0 to other custom IP: custom_design_32_1 on the stratix 10 development board.

Anybody please verify and suggest me that , Is connections are ok ?


Regards,
Anil
Attached Images
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Documentation for non-latest Intel FPGA SDK for OpenCL

May 8, 2018, 5:59 am
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Hello,

I recently got a Nallatech board whose BSP was created with tools v.17.1.
Therefore I plan to use same SDK version and review the corresponding documentation.
However, the documentation I could find online on the Intel/Altera websites corresponds to the latest one (18.0):

* https://www.altera.com/products/desi...l/support.html
* http://dl.altera.com/opencl/17.1/?ed...d_manager=dlm3

I was wondering if someone knows a page where I can find all documentation related specifically to the v.17.1.

Thanks!

Leo
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I need help about quartus

May 8, 2018, 7:45 am
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Hi falles, I am writing you from Turkiye
I have to make a quartus project
maybe it is very simple but I dont know anything about quartus and FPGA
I need to design a 3 bits multiplier in quartus
I am posting the circuit on paper
how can I design it in quartus
if there is someone in the forum who knows about it, pls help me
thank you
have a nice days guys

Attached Images
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Hard Ip Core and power

May 8, 2018, 7:47 am
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Good afternoon, colleagues.


I have Stratix V, I have been trying for a long time to run hard ip core pcie (Constantly get lsmsm = 0000).

Today I decided to measure the tension on the pins. And I found out that in 2 out of 6 pins VCCHSSI_L (Transceiver PCS power supply (left side)) there is no voltage. How do you think, can this be the reason for the launch problem?
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Issues with changing to a larger memory CPLD

May 8, 2018, 8:06 am
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I have project that I was using 5M570ZT144C5N. I was running out of logic elements and I had to change to 5M1270ZT144C5N. I recompiled with the new CPLD selected and deployed to the target without an issue. However, the project now is using the 5M1270ZT144C5N and does not behave the same when using the 5M570ZT144C5N. What do I need to do to fix this?

Thank You
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Missing NIOS II Hardware in run configurations

May 8, 2018, 8:40 am
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Folks,
I have inherited a mature design from a previous project. The target is a DE0_nano, with a NIOS II/f processor in the design. My qts version is 11.1, fully licensed, windows 10 env. The project builds without error. When I launch eclipse, it builds the BSP and the processor application code. What is missing is a NIOS II hardware target when I bring up the run or debug configurations dialog. I cant load and run the project on the Nios using eclipse.

I have built everything from scratch, rebuilt the BSP and this selection is not in my configuration. A developer using the exact same project directory with the exact tools can bring eclipse up and the NIOS II Hardware is available. I can program the FPGA OK, and download and run the NIOS using the command line, so I kno that the JTAG chain is intact and working.

Question: How does eclipse kno that a NIOS II is "out there" as a viable target to load and debug?

Thanks,
Ed
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FPGA Cyclone V

May 8, 2018, 10:41 am
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Hello,
Actually, I have a project with an FPGA, I installed Quartus II 12.1 Subscription Edition without license from the original CD.
I try to do my simple application and everything was good until the compilation was successful, but when I connect my board with a USB - blaster. I try to charge the file" .sof " I don't find it. What's the problem?
Is it related to license or something like that?
My board is cyclone V ref:5CSEMA5F31C6N and I choose 5CSEMA5F31C6 in QuartusII
Is there a deiiference in the device?
Please help me, I need to start my project
There are some attachments to show u more details.
Thanks.
Attached Images
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Critical Path in Loop

May 8, 2018, 11:09 am
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I'm trying to the use the details of the loop analysis report to decrease the ii of a loop. Unfortunately I can't find a good explanation about some of the details. I've posted the output of part of the report below, followed by some questions.
Code:
The critical path that prevented successful II = 1 scheduling:
Question 1) - The first bullet says the number of nodes in critical path is beyond what the compiler captured, and the top 13 FAILING does are listed. Some of the bullets below that are > 1 clock cycle, some are < 1 clock cycle. Is each bullet an independent critical path? If so, aren't the paths < 1 NOT failing? Am I missing something here? If I know I can focus on the bullets that are > 1 to get to an ii of 1 it would be easier.

Question 2) - Bullet 1 indicates a 1.1 clock cycle select operation on the "stallRead" variable. I can't fathom how this logic can't be accomplished in a single clock cycle. See the code segment below. I want to read from a channel on every loop, until an end of frame flag is set in the read data. At that point, stall for 6 clock cycles then then start reading again.

Code:
uchar stallRead = 0;       
while(1)
    {       
        if (stallRead == 0)
        {                   
            rxData      = read_channel_intel(TOCLIENT);
            rxWord[0]  = rxData.data;           
            rxStatus[0] = parseStatus(rxData.header);
            if (rxStatus[0].eop) //if we hit a end of frame flag, stall for a few clock cycles
                stallRead = 0x40;
        }
        else
            stallMacRead = stallMacRead >> 1;


                case statement and other logic......
Thanks, any suggestions or pointing to examples or documentation is appreciated.
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Does SignalTap work with other ICs in the JTAG chain?

May 8, 2018, 12:57 pm
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Does Quartus II SignalTap work with ICs in the JTAG chain other than the Altera FPGA where SignalTap is being utilized? I get "Invalid JTAG configuration" in the SignalTap II Logic Analyzer stp window.
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NIOS with Configuration via Protocol (CvP) Design

May 8, 2018, 1:21 pm
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I am currently working to implement a NIOS on a CvP design on the Peripheral portion.

I've taken the .sof, which contains the peripheral and core portions of my CvP design and loaded it onto my Stratix 5.

I am running into issues when attempting to run my application, I get the error: No Nios II target connection paths were located. Check connections and that a Nios II .sof is downloaded.

After seeing this failure, I stripped down my project to just the NIOS II, and it runs a hello world application fine using the same clk and reset pins.

Does anyone have any idea on what could be going on?

Thanks.
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Driving Ladder DAC

May 8, 2018, 5:14 pm
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Hi,

Im trying to drive a resistor ladder DAC from my DE-1 SOC board, despite of my DAC being very accurate im getting somewhat shotty results.
The setup is relatively simple driving the resistors directly from the board. Right now im using plain old 3.3v ttl to drive it.

I was wondering what output standard is best used, and if I can drive Z to it without any troubles?




Kind Regards,
Camper.
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QuartusII 18.0 - number of processors used during compilation question

May 8, 2018, 7:09 pm
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Hi,
I'm wondering whether in Quartus II 18.0 parallel processor usage is (again) limited to full versions, i.e. not available in the lite (free) Edition.
Under Settings => Compilation Settings => Parallel compilaton moving the mouse pointer to either option in section parallel compilation it shows the hint "to use this feature you must purchase a full featured Edition of the Quartus Prime Software".
Starting the compilation, in the message window there is the message "Info (20032): Parallel compilation is enabled and will use up to 4 processors"
Contrary to this in the flow report, only use of one processor of my QuadCore is shown (in 17.1 all four were stated to be used).

Is therefore the info in the message window false and Intel PSG "advertises" v18.0 to reduce compilaton times and memory usage, but does not mention this benefits now require to spend $2,995 ? :confused:

Thus changing from 17.1 to 18.0 in free Edition is more a drawback in Performance.. :(

Kind regards, Carlhermann
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What is VTAP10?

May 8, 2018, 7:52 pm
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Hi guys. So I have my Max 10 development kit installed and am checking to be sure I have the drivers installed properly.
Quartus Prime 17.1 is running fine. :cool:

But now I have what seems to be a problem.

The Intel Max10 Dev board runs the included board software OK, when it comes to using the programmer, I have questions.

I have been able to get a simple design to program and run, but only after fiddling with 'auto-detect', and removing a detected hardware called VTAP10.
There is no VTAP10 showing up in the tutorial demo I followed, but the tutorial was using 15.0.

I could use a little help.
What is VTAP10 and how does it fit into the picture?
Is the VTAP10 hardware part of the Altera/Intel Development board, or am I looking at a bad USB-blaster driver install or other mess up?
What documentation should I reference to understand this part better? Thanks for your help.
↧
↧

Upgrade Quartus 17.0 to Quartus 18.0 issue

May 9, 2018, 1:59 am
$
0
0
Hi everyone,
I have a problem with Quartus 18.0 standard version.
If I compile my project on Quartus 17.0 it needs about 75 minutes, on the other hand after the upgrade to 18.0 standard version it needs 225 minutes, it's a huge difference.


The settings of the quartus 17.0 and 18.0 are the same, both FPGA codes works. However, I don't understand why.


Some advices?

Just tried to delete the database nothing's changed.
↧

Arria 10 TSE with GXB

May 9, 2018, 2:21 am
$
0
0
Dear Sir,

I am working on a design on the DE5A-NET-DDR4. But it is not for 10G or 40G Ethernet.
It is a Gigabit Ethernet design. It is from our old project. It was working well on the
Arria 5 starter kit. It uses a TSE with LVDS design for the PCS and PMA. I am not
modify it onto the DE5 board, by modifying the PMA into GXB. In addition, the GXB needs
two additional clocks, tx_serial_clk and rx_cdr_refclk. I have used an fPLL to generate
a mcgb_serial_clk for the tx_serial_clk and a 125Mhz from input pin (it is from a clock
synthesizer si5340). The compilation is ok now. The PCS configuration is follow the
TSE manual to set as below.

0x13 = 0x13
0x12 = 0x12d0
0x00 = 0x5140
0x14 = 0x0000
0x00 = 0xd140

The attached jpg file is the verilog code for the tse connection check. I don't know why the
pcs loopback is not working.


Regards,


Peter Chang


Attached Images
↧

Need for Shelf life & Packing Type of the following MPN's.

May 9, 2018, 3:06 am
$
0
0
Hi,

This is Prachi from Flex.

We are currently working with one of our manufacturing plant to collect required Data.

Site: Zhuhai

Please help us to provide: -


· Packing type (If tray – please provide – whether Hard tray or Soft tray), & Shelf life

Hard Tray means “It is a plastic chip tray of conductive polystyrene and antistatic ABS. Customer will be satisfied quality, price and delivery of ADY products since our corporate factory in Taiwan control the total operation from mold design, mold assemble, production, inspection to packing by themselves”
&
Soft Tray means “It is a tray formed by vaccuming resin sheet. SOFT TRAY is designed and manufactured according to the part shape by the best size”


Kindly provide the datasheet for the same.

Customer Flex P/N Description MFR MPN Packing type Shelf life
Cisco CISH-16-100294-01 IC-FPGA,5AGXMA5D4-4.0,FCBGA,67 ALTERA 5AGXMA5D4F27C4N
Cisco CISH-16-100383-01 IC-FPGA,EP4CE40-8.0,FBGA,780 P ALTERA EP4CE40F29C8N
Cisco CISH-16-100521-01 IC-FPGA,5AGXMA7G4-5.0,FCBGA,89 ALTERA 5AGXMA7G4F31I5NAB
Cisco CISH-16-100818-01 IC-FPGA,5AGXFB3H4-5.0,FCBGA,11 ALTERA 5AGXFB3H4F35I5G
Cisco CISH-16-4323-01 IC,PLD-FPGA,EP4CGX22C-7,FBGA32 ALTERA EP4CGX22CF19I7N
Cisco CISH-16-4426-01 IC-FPGA,5AGTFD7K3-5.0,FCBGA,15 ALTERA 5AGTFD7K3F40I5NAC
Cisco CISH-16-4405-01 IC-FPGA,EP4CGX75D-7.0,FBGA,672 ALTERA EP4CGX75DF27C6N
Cisco CISH-16-4174-01 IC,PLD-FPGA,EP4CGX30C-8, FBGA4 ALTERA EP4CGX30CF23C8N
Cisco CISH-16-4243-01 IC,PLD-FPGA,EP4CGX50C-8,FBGA48 ALTERA EP4CGX50CF23C8N
Cisco CISH-16-101088-01 IC-FPGA,10AX032H4-3.0,FPBGA,11 ALTERA 10AX032H4F34E3SG


· Shelf life

Customer Flex P/N Description MFR MPN Shelf life
Cisco CISH-16-3281-02 IC-FPGA,EP2C20-8,FBGA256,PB-Fr ALTERA EP2C20F256C8N
Cisco CISH-16-4088-01 IC,PLD-FPGA,EP2AGX45CU17I3N,I- ALTERA EP2AGX45CU17I3G
Cisco CISH-16-3065-01 IC-FPGA,EP1C3-8,TQFP144 ALTERA EP1C3T144C8N

Please note that this is the critical project we are handling for Zhuhai site. Any delay in providing the data will affect in receiving the part.
Also there are possibilities of rejection in the shipment.
Hence we request you to provide the data as early as possible.

Let me know for any help.
Thank you.
↧
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