Is sGDMA integration correct in this SoC ??

May 9, 2018, 6:44 am

≫ Next: Setting VCCPD in the Pin Planner or in any other way

≪ Previous: Need for Shelf life & Packing Type of the following MPN's.

Hello all,

I am using modular scatter-gather DMA core to transfer data from my custom IP: custom_design_32_0 to other custom IP: custom_design_32_1 on the stratix 10 development board.

Anybody please verify and suggest me that , Is connections are ok ?

Regards,
Anil

Attached Images

sgdma_ip_integration1.jpg (19.3 KB)

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Setting VCCPD in the Pin Planner or in any other way

May 9, 2018, 8:41 am

≫ Next: Triple Speed Ethernet - Send to PC?

≪ Previous: Is sGDMA integration correct in this SoC ??

Hello,

My problem is that the standard setting of VCCPD for my project is 2.5V and I need to set it for certain banks to 3.3V. I have looked through the pin planner, and the device settings and I haven't found a single setting to change it.

I need to change it, as I need 3.3V LVCMOS output, which requires 3.3V VCCIO, which in turn requires setting the VCCPD for those banks to 3.3V.

I know this is a blatant question, but I really haven't found how to do it anywhere.

Thank you and have a nice day,

Tibor

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Triple Speed Ethernet - Send to PC?

May 9, 2018, 8:49 am

≫ Next: DE10-Lite Video problem drawing a pixel

≪ Previous: Setting VCCPD in the Pin Planner or in any other way

Hello all.

I need help on further testing with the 'Using Triple Speed Ethernet on DE2-115 Boards' tutorial.
(which is the one on the link below)
ftp://ftp.altera.com/up/pub/Altera_M...d_ethernet.pdf

Right now, I am trying to send data to PC (a laptop) by connecting ethernet cable between Ethernet Port 1 of DE2-115 Board and PC's LAN port. I've done everything as the same as the tutorial, and from what I understand, data will be sent from Ethernet1 port of the board to PC, where I will use Wireshark to see the incoming packets.

However, I don't see anything coming in to PC (looking at Wireshark) when I send packets. Except the periodic standard queries and initialization. I input strings in Altera Monitor Program, press enter to send, but nothing coming in.

So the question here is...
if I follow the 'Using Triple Speed Ethernet on DE2-115 Boards' tutorial,
connect Ethernet1 port of DE2-115 board with PC's LAN port,
send data (using Altera Monitor Program) through LAN Cable,

packets should be received normally on PC, right?
Or are there TSE register configurations I must do to make packets be acknowledged by PC?
Has anyone done similar project? What do I need to do?

Thanks in advance.

+) I assume that the cable itself does not have any problems, because port0-port1 loopback works for me.

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DE10-Lite Video problem drawing a pixel

May 9, 2018, 11:11 am

≫ Next: Could not acquire a valid license for the Intel(R) FPGA SDK for OpenCL(TM).

≪ Previous: Triple Speed Ethernet - Send to PC?

Hi, I'm making a project for my university and I'm working on a Videogame with a DE10-Lite.
I'm trying to get the video processing working and everything is fine except one problem:

If I try to draw the 0,0 pixel with a color containing a blue signal (Blue component different from 0) the video goes crazy and everything starts flickering

If I draw a red or yellow color on 0,0 everything is fine. As long as the Blue bits of the pixel 0,0 are set to 0 it works.

Here you can see:

No blue on 0,0 pixel and the video is fine:
https://ibb.co/dWmdTy

I put 0x0001 on the 0,0 pixel and madness happens:
https://ibb.co/gwpMgJ

I'm using a 16 bit Pixel buffer with DMA reading SDRAM linked with other video IPS. The output signal goes to a VGA monitor.

Here is the embedded system built with Qsys:

If I draw blue on the 0,0 pixel, even the video signal coming from the char buffer is heavily disturbed. I can't manage to understand what could be causing the problem.

Any help is appreciated, thanks.

Attached Images

17990990_1852039471727200_7338948595048312338_n.jpg (169.6 KB)

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Could not acquire a valid license for the Intel(R) FPGA SDK for OpenCL(TM).

May 9, 2018, 2:52 pm

≫ Next: Documentation for non-latest Intel FPGA SDK for OpenCL

≪ Previous: DE10-Lite Video problem drawing a pixel

Hi,

I got this error when I try to compile vector_add program according to the manual. This is the command I use and here is what i got.

[root@machine vector_add]# aoc device/vector_add.cl -o bin/vector_add.aocx --board de5a_net_i2

Could not acquire a valid license for the Intel(R) FPGA SDK for OpenCL(TM).
Error: Verilog generator FAILED.
Refer to vector_add/vector_add.log for details.

I am using CentOS 7.4 and I have Quartus prime 16.1 and Open CL 16.1 installed. I have got the license and set up the env variable and have no problem running the quartus application itself. My only problem is that it doesn't recognize the OpenCL license.
BTW, I have read the post and the solution given below but it didn't solve my problem! Maybe I am not doing it correctly! It would be nice if someone tell how I have to find the NIC ID to set for the dummy port ? or if you suggest other solutions that can solve the problem. BTW, I tried newer quartus version but I had problem using them with the board I have. It seems 16.1 is the only version that I can install the board.
https://www.altera.com/support/suppo...ntos-7-x-.html

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Documentation for non-latest Intel FPGA SDK for OpenCL

May 8, 2018, 5:59 am

≫ Next: I need help about quartus

≪ Previous: Could not acquire a valid license for the Intel(R) FPGA SDK for OpenCL(TM).

Hello,

I recently got a Nallatech board whose BSP was created with tools v.17.1.
Therefore I plan to use same SDK version and review the corresponding documentation.
However, the documentation I could find online on the Intel/Altera websites corresponds to the latest one (18.0):

* https://www.altera.com/products/desi...l/support.html
* http://dl.altera.com/opencl/17.1/?ed...d_manager=dlm3

I was wondering if someone knows a page where I can find all documentation related specifically to the v.17.1.

Thanks!

Leo

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I need help about quartus

May 8, 2018, 7:45 am

≫ Next: Hard Ip Core and power

≪ Previous: Documentation for non-latest Intel FPGA SDK for OpenCL

Hi falles, I am writing you from Turkiye
I have to make a quartus project
maybe it is very simple but I dont know anything about quartus and FPGA
I need to design a 3 bits multiplier in quartus
I am posting the circuit on paper
how can I design it in quartus
if there is someone in the forum who knows about it, pls help me
thank you
have a nice days guys

Attached Images

multiplier.jpg (71.3 KB)

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Hard Ip Core and power

May 8, 2018, 7:47 am

≫ Next: Issues with changing to a larger memory CPLD

≪ Previous: I need help about quartus

Good afternoon, colleagues.

I have Stratix V, I have been trying for a long time to run hard ip core pcie (Constantly get lsmsm = 0000).

Today I decided to measure the tension on the pins. And I found out that in 2 out of 6 pins VCCHSSI_L (Transceiver PCS power supply (left side)) there is no voltage. How do you think, can this be the reason for the launch problem?

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Issues with changing to a larger memory CPLD

May 8, 2018, 8:06 am

≫ Next: Missing NIOS II Hardware in run configurations

≪ Previous: Hard Ip Core and power

I have project that I was using 5M570ZT144C5N. I was running out of logic elements and I had to change to 5M1270ZT144C5N. I recompiled with the new CPLD selected and deployed to the target without an issue. However, the project now is using the 5M1270ZT144C5N and does not behave the same when using the 5M570ZT144C5N. What do I need to do to fix this?

Thank You

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Missing NIOS II Hardware in run configurations

May 8, 2018, 8:40 am

≫ Next: FPGA Cyclone V

≪ Previous: Issues with changing to a larger memory CPLD

Folks,
I have inherited a mature design from a previous project. The target is a DE0_nano, with a NIOS II/f processor in the design. My qts version is 11.1, fully licensed, windows 10 env. The project builds without error. When I launch eclipse, it builds the BSP and the processor application code. What is missing is a NIOS II hardware target when I bring up the run or debug configurations dialog. I cant load and run the project on the Nios using eclipse.

I have built everything from scratch, rebuilt the BSP and this selection is not in my configuration. A developer using the exact same project directory with the exact tools can bring eclipse up and the NIOS II Hardware is available. I can program the FPGA OK, and download and run the NIOS using the command line, so I kno that the JTAG chain is intact and working.

Question: How does eclipse kno that a NIOS II is "out there" as a viable target to load and debug?

Thanks,
Ed

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FPGA Cyclone V

May 8, 2018, 10:41 am

≫ Next: Critical Path in Loop

≪ Previous: Missing NIOS II Hardware in run configurations

Hello,
Actually, I have a project with an FPGA, I installed Quartus II 12.1 Subscription Edition without license from the original CD.
I try to do my simple application and everything was good until the compilation was successful, but when I connect my board with a USB - blaster. I try to charge the file" .sof " I don't find it. What's the problem?
Is it related to license or something like that?
My board is cyclone V ref:5CSEMA5F31C6N and I choose 5CSEMA5F31C6 in QuartusII
Is there a deiiference in the device?
Please help me, I need to start my project
There are some attachments to show u more details.
Thanks.

Attached Images

photo1.jpg (20.8 KB)
photo2.jpg (20.9 KB)
photo3.jpg (20.7 KB)

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Critical Path in Loop

May 8, 2018, 11:09 am

≫ Next: Does SignalTap work with other ICs in the JTAG chain?

≪ Previous: FPGA Cyclone V

I'm trying to the use the details of the loop analysis report to decrease the ii of a loop. Unfortunately I can't find a good explanation about some of the details. I've posted the output of part of the report below, followed by some questions.

Code:

The critical path that prevented successful II = 1 scheduling:

Number of nodes in critical path exceeded what the compiler has captured. Only the top 13 failing nodes are listed.

1.1 clock cycle Select Operation (udpip.cl: 195, udpip.cl: 199)
1.1 clock cycle Select Operation (udpip.cl: 144, udpip.cl: 222, udpip.cl: 362, udpip.cl: 366, udpip.cl: 371, udpip.cl: 388, udpip.cl: 390)
1.1 clock cycle Select Operation (udpip.cl: 191, udpip.cl: 192)
1 clock cycle Left Shift Operation (udpip.cl: 195)
0.22 clock cycles 32-bit Integer Add Operation (udpip.cl: 1220, udpip.cl: 1228, udpip.cl: 1235)
0.22 clock cycles 32-bit Integer Add Operation (udpip.cl: 1220, udpip.cl: 1235)
0.22 clock cycles 32-bit Integer Add Operation (udpip.cl: 1235)
.........

Question 1) - The first bullet says the number of nodes in critical path is beyond what the compiler captured, and the top 13 FAILING does are listed. Some of the bullets below that are > 1 clock cycle, some are < 1 clock cycle. Is each bullet an independent critical path? If so, aren't the paths < 1 NOT failing? Am I missing something here? If I know I can focus on the bullets that are > 1 to get to an ii of 1 it would be easier.

Question 2) - Bullet 1 indicates a 1.1 clock cycle select operation on the "stallRead" variable. I can't fathom how this logic can't be accomplished in a single clock cycle. See the code segment below. I want to read from a channel on every loop, until an end of frame flag is set in the read data. At that point, stall for 6 clock cycles then then start reading again.

Code:

uchar stallRead = 0;        

while(1)

    {        

        if (stallRead == 0)

        {                    

            rxData      = read_channel_intel(TOCLIENT);

            rxWord[0]   = rxData.data;            

            rxStatus[0] = parseStatus(rxData.header);

            if (rxStatus[0].eop) //if we hit a end of frame flag, stall for a few clock cycles

                stallRead = 0x40;

        }

        else

            stallMacRead = stallMacRead >> 1;





                case statement and other logic......

Thanks, any suggestions or pointing to examples or documentation is appreciated.

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Does SignalTap work with other ICs in the JTAG chain?

May 8, 2018, 12:57 pm

≫ Next: NIOS with Configuration via Protocol (CvP) Design

≪ Previous: Critical Path in Loop

Does Quartus II SignalTap work with ICs in the JTAG chain other than the Altera FPGA where SignalTap is being utilized? I get "Invalid JTAG configuration" in the SignalTap II Logic Analyzer stp window.

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NIOS with Configuration via Protocol (CvP) Design

May 8, 2018, 1:21 pm

≫ Next: Driving Ladder DAC

≪ Previous: Does SignalTap work with other ICs in the JTAG chain?

I am currently working to implement a NIOS on a CvP design on the Peripheral portion.

I've taken the .sof, which contains the peripheral and core portions of my CvP design and loaded it onto my Stratix 5.

I am running into issues when attempting to run my application, I get the error: No Nios II target connection paths were located. Check connections and that a Nios II .sof is downloaded.

After seeing this failure, I stripped down my project to just the NIOS II, and it runs a hello world application fine using the same clk and reset pins.

Does anyone have any idea on what could be going on?

Thanks.

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Driving Ladder DAC

May 8, 2018, 5:14 pm

≫ Next: QuartusII 18.0 - number of processors used during compilation question

≪ Previous: NIOS with Configuration via Protocol (CvP) Design

Hi,

Im trying to drive a resistor ladder DAC from my DE-1 SOC board, despite of my DAC being very accurate im getting somewhat shotty results.
The setup is relatively simple driving the resistors directly from the board. Right now im using plain old 3.3v ttl to drive it.

I was wondering what output standard is best used, and if I can drive Z to it without any troubles?

Kind Regards,
Camper.

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QuartusII 18.0 - number of processors used during compilation question

May 8, 2018, 7:09 pm

≫ Next: What is VTAP10?

≪ Previous: Driving Ladder DAC

Hi,
I'm wondering whether in Quartus II 18.0 parallel processor usage is (again) limited to full versions, i.e. not available in the lite (free) Edition.
Under Settings => Compilation Settings => Parallel compilaton moving the mouse pointer to either option in section parallel compilation it shows the hint "to use this feature you must purchase a full featured Edition of the Quartus Prime Software".
Starting the compilation, in the message window there is the message "Info (20032): Parallel compilation is enabled and will use up to 4 processors"
Contrary to this in the flow report, only use of one processor of my QuadCore is shown (in 17.1 all four were stated to be used).

Is therefore the info in the message window false and Intel PSG "advertises" v18.0 to reduce compilaton times and memory usage, but does not mention this benefits now require to spend $2,995 ? :confused:

Thus changing from 17.1 to 18.0 in free Edition is more a drawback in Performance.. :(

Kind regards, Carlhermann

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What is VTAP10?

May 8, 2018, 7:52 pm

≫ Next: Upgrade Quartus 17.0 to Quartus 18.0 issue

≪ Previous: QuartusII 18.0 - number of processors used during compilation question

Hi guys. So I have my Max 10 development kit installed and am checking to be sure I have the drivers installed properly.

Quartus Prime 17.1 is running fine. :cool:

But now I have what seems to be a problem.

The Intel Max10 Dev board runs the included board software OK, when it comes to using the programmer, I have questions.

I have been able to get a simple design to program and run, but only after fiddling with 'auto-detect', and removing a detected hardware called VTAP10.
There is no VTAP10 showing up in the tutorial demo I followed, but the tutorial was using 15.0.

I could use a little help.

What is VTAP10 and how does it fit into the picture?
Is the VTAP10 hardware part of the Altera/Intel Development board, or am I looking at a bad USB-blaster driver install or other mess up?
What documentation should I reference to understand this part better? Thanks for your help.

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Upgrade Quartus 17.0 to Quartus 18.0 issue

May 9, 2018, 1:59 am

≫ Next: Arria 10 TSE with GXB

≪ Previous: What is VTAP10?

Hi everyone,
I have a problem with Quartus 18.0 standard version.
If I compile my project on Quartus 17.0 it needs about 75 minutes, on the other hand after the upgrade to 18.0 standard version it needs 225 minutes, it's a huge difference.

The settings of the quartus 17.0 and 18.0 are the same, both FPGA codes works. However, I don't understand why.

Some advices?

Just tried to delete the database nothing's changed.

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Arria 10 TSE with GXB

May 9, 2018, 2:21 am

≫ Next: Need for Shelf life & Packing Type of the following MPN's.

≪ Previous: Upgrade Quartus 17.0 to Quartus 18.0 issue

Dear Sir,

I am working on a design on the DE5A-NET-DDR4. But it is not for 10G or 40G Ethernet.
It is a Gigabit Ethernet design. It is from our old project. It was working well on the
Arria 5 starter kit. It uses a TSE with LVDS design for the PCS and PMA. I am not
modify it onto the DE5 board, by modifying the PMA into GXB. In addition, the GXB needs
two additional clocks, tx_serial_clk and rx_cdr_refclk. I have used an fPLL to generate
a mcgb_serial_clk for the tx_serial_clk and a 125Mhz from input pin (it is from a clock
synthesizer si5340). The compilation is ok now. The PCS configuration is follow the
TSE manual to set as below.

0x13 = 0x13
0x12 = 0x12d0
0x00 = 0x5140
0x14 = 0x0000
0x00 = 0xd140

The attached jpg file is the verilog code for the tse connection check. I don't know why the
pcs loopback is not working.

Regards,

Peter Chang

Attached Images