Quantcast
Channel: Altera Forums
Viewing all 19390 articles
Browse latest View live
↧

Is sGDMA integration correct in this SoC ??

May 9, 2018, 6:44 am
$
0
0
Hello all,

I am using modular scatter-gather DMA core to transfer data from my custom IP: custom_design_32_0 to other custom IP: custom_design_32_1 on the stratix 10 development board.

Anybody please verify and suggest me that , Is connections are ok ?


Regards,
Anil
Attached Images
↧
Search

Setting VCCPD in the Pin Planner or in any other way

May 9, 2018, 8:41 am
$
0
0
Hello,

My problem is that the standard setting of VCCPD for my project is 2.5V and I need to set it for certain banks to 3.3V. I have looked through the pin planner, and the device settings and I haven't found a single setting to change it.

I need to change it, as I need 3.3V LVCMOS output, which requires 3.3V VCCIO, which in turn requires setting the VCCPD for those banks to 3.3V.

I know this is a blatant question, but I really haven't found how to do it anywhere.

Thank you and have a nice day,

Tibor
↧
↧

Triple Speed Ethernet - Send to PC?

May 9, 2018, 8:49 am
$
0
0
Hello all.

I need help on further testing with the 'Using Triple Speed Ethernet on DE2-115 Boards' tutorial.
(which is the one on the link below)
ftp://ftp.altera.com/up/pub/Altera_M...d_ethernet.pdf

Right now, I am trying to send data to PC (a laptop) by connecting ethernet cable between Ethernet Port 1 of DE2-115 Board and PC's LAN port. I've done everything as the same as the tutorial, and from what I understand, data will be sent from Ethernet1 port of the board to PC, where I will use Wireshark to see the incoming packets.

However, I don't see anything coming in to PC (looking at Wireshark) when I send packets. Except the periodic standard queries and initialization. I input strings in Altera Monitor Program, press enter to send, but nothing coming in.


So the question here is...
if I follow the 'Using Triple Speed Ethernet on DE2-115 Boards' tutorial,
connect Ethernet1 port of DE2-115 board with PC's LAN port,
send data (using Altera Monitor Program) through LAN Cable,

packets should be received normally on PC, right?
Or are there TSE register configurations I must do to make packets be acknowledged by PC?
Has anyone done similar project? What do I need to do?

Thanks in advance.


+) I assume that the cable itself does not have any problems, because port0-port1 loopback works for me.
↧

DE10-Lite Video problem drawing a pixel

May 9, 2018, 11:11 am
$
0
0
Hi, I'm making a project for my university and I'm working on a Videogame with a DE10-Lite.
I'm trying to get the video processing working and everything is fine except one problem:

If I try to draw the 0,0 pixel with a color containing a blue signal (Blue component different from 0) the video goes crazy and everything starts flickering

If I draw a red or yellow color on 0,0 everything is fine. As long as the Blue bits of the pixel 0,0 are set to 0 it works.

Here you can see:

No blue on 0,0 pixel and the video is fine:
https://ibb.co/dWmdTy

I put 0x0001 on the 0,0 pixel and madness happens:
https://ibb.co/gwpMgJ

I'm using a 16 bit Pixel buffer with DMA reading SDRAM linked with other video IPS. The output signal goes to a VGA monitor.

Here is the embedded system built with Qsys:


If I draw blue on the 0,0 pixel, even the video signal coming from the char buffer is heavily disturbed. I can't manage to understand what could be causing the problem.

Any help is appreciated, thanks.
↧

Could not acquire a valid license for the Intel(R) FPGA SDK for OpenCL(TM).

May 9, 2018, 2:52 pm
$
0
0
Hi,

I got this error when I try to compile vector_add program according to the manual. This is the command I use and here is what i got.

[root@machine vector_add]# aoc device/vector_add.cl -o bin/vector_add.aocx --board de5a_net_i2

Could not acquire a valid license for the Intel(R) FPGA SDK for OpenCL(TM).
Error: Verilog generator FAILED.
Refer to vector_add/vector_add.log for details.

I am using CentOS 7.4 and I have Quartus prime 16.1 and Open CL 16.1 installed. I have got the license and set up the env variable and have no problem running the quartus application itself. My only problem is that it doesn't recognize the OpenCL license.
BTW, I have read the post and the solution given below but it didn't solve my problem! Maybe I am not doing it correctly! It would be nice if someone tell how I have to find the NIC ID to set for the dummy port ? or if you suggest other solutions that can solve the problem. BTW, I tried newer quartus version but I had problem using them with the board I have. It seems 16.1 is the only version that I can install the board.
https://www.altera.com/support/suppo...ntos-7-x-.html
↧
↧

Request for Data

May 9, 2018, 11:59 pm
$
0
0
Hi,

This is Chaitanya from Flex.
We are currently working with one of our manufacturing plant to collect attribute information.

Site: Zhuhai

Please help us to provide,

  • Shelf Life from the Date of manufacturing
  • Packing type (If it is Tray please confirm whether it is Soft Tray or Hard Tray)
  • Overall Height of the Component


Customer Flex P/N Description MFG MPN Packing type Comp Package thickness mm (Nominal)
Avaya AVIH-93032-00011 IC FLASH MEMORY SMD EPCS1 1MBi ALTERA EPCS1SI8N
Cisco CISH-16-100021-01 IC-FPGA,EP3C120,8,FBGA-780,C-T ALTERA EP3C120F780C8N
Cisco CISH-16-100041-01 IC ,PLD-CPLD ,5M40Z-5,MBGA64,4 ALTERA 5M40ZM64C5N
Cisco CISH-16-100071-01 IC-FPGA,5AGXFB3,ALTERA ARRIA V ALTERA 5AGXFB3H4F35C4G
Cisco CISH-16-100071-01 IC-FPGA,5AGXFB3,ALTERA ARRIA V ALTERA 5AGXFB3H4F35C4N
Cisco CISH-16-100205-01 IC,PLD-FPGA,5AGXBB1D4-4,FCBGA1 ALTERA 5AGXBB1D4F35C4GAA
Cisco CISH-16-100205-01 IC,PLD-FPGA,5AGXBB1D4-4,FCBGA1 ALTERA 5AGXBB1D4F35C4NAA
Cisco CISH-16-100220-01 IC, PLD-FPGA, EP4CE10F17C-8, F ALTERA EP4CE10F17C8N
Cisco CISH-16-100221-01 IC,PLD-CPLD,5M570Z-5,MBGA100,1 ALTERA 5M570ZM100C5N
Cisco CISH-16-100294-01 IC-FPGA,5AGXMA5D4-4.0,FCBGA,67 ALTERA 5AGXMA5D4F27C4G
Cisco CISH-16-100467-01 IC-CPROM,EPCQ16,SOIC,8 P,1.27 ALTERA EPCQ16SI8N
Cisco CISH-16-100864-01 IC-FPGA,10AX027H4-3.0,FBGA,115 ALTERA 10AX027H4F34E3SG
Cisco CISH-16-100909-01 IC-FPGA,EP4CE6-7.0,UBGA,256 P, ALTERA EP4CE6U14I7N
Cisco CISH-16-4405-01 IC,PLD-FPGA,EP4CGX75D-7,FBGA67 ALTERA EP4CGX75DF27C7N
Broadcom EMXH-P001323 IC, EPM1270 CPLD, 3.3V, FBGA-2 ALTERA EPM1270F256C5N
F5 Networking FFVH-ICS-0461-00 IC,CPLD,ALTERA MAX II EPM2210, ALTERA EPM2210F256C5N
F5 Networking FFVH-ICS-0756-00 IC, FPGA, ALTERA STRATIX V, 5S ALTERA 5SGXMA3H2F35C2N
F5 Networking FFVH-ICS-0765-00 IC, CPLD, ALTERA MAX V 5M2210Z ALTERA 5M2210ZF256C5N
F5 Networking FFVH-PWR-0299-00 PWR, DC-DC CONVERTER, 12A POWE ALTERA EN63A0QI

Please note that this is the critical project we are handling for Zhuhai site. Any delay in providing the data will affect in receiving the part.
Also there are possibilities of rejection in the shipment.
Hence we request you to provide the data as early as possible.
↧

Path too long and error while deleting.

May 10, 2018, 1:20 am
$
0
0
Is there any powerful tool which delete files and folders with long paths? I need some idea.
↧

Erased CFM0 on Max 10 - Can't find JTAG Connection

May 10, 2018, 3:53 am
$
0
0
I am running some tests on the Max 10, performing read/write/erase operations on the the UFM and CFM. Once of these tasks was to erase the sector 5, containing Image 0, to check that the device would default to image 2.

It appeared that this test was succesful (the device no longer is able to load into Imgae 0). However, I am not able to connect to the Max 10 via the JTAG interface to reprogram it.



Using the Quartus 17.1 Programmer, trying to "Auto Detect" the device gives the following error:
- "Unable to scan device chain. Hardware is not connected."



The USB Blaster II driver identifies the device when it is plugged in and switched on. However, it seems to keep sending messages switching between "Device Attached" and "Device Detached" while the Max 10 is plugged in, switched on and left untouched.



It seems like there is a problem with the JTAG connection. I have tried a different Max 10 Development Board on the same PC, with exactly the same setupand it seems to be working fine. The only difference between the two development boards as I can see is that I have completely erased Image 0 from the CFM.


Is it possible that this may have cause some issues with the JTAG connection to the Max 10?


Cheers.
↧
Search

State Machine Viewer - missing transition

May 10, 2018, 5:19 am
$
0
0
Hello every one,
can you explain me why I get different state transition diagram from relatively the same VHDL?
Here is the code:
1)
if rx_bit_index < 7 then
rx_bit_index <= rx_bit_index + 1;
rx_state <= s_rx_data_bits;
else
rx_bit_index <= 0;
rx_state <= s_rx_stop_bit;
end if;
2)
if rx_bit_index = 7 then
rx_bit_index <= 0;
rx_state <= s_rx_stop_bit;
else
rx_bit_index <= rx_bit_index + 1;
rx_state <= s_rx_data_bits;
end if;
and here the state transition:
New Bitmap Image1 - Copy.bmp
New Bitmap Image1.bmp

Regards,
Emil
Attached Images
↧
↧

SISO testbench and waveform HELP

May 10, 2018, 6:58 am
$
0
0
Hello, i am new to VHDL and i want some directions.
I want to make a Serial in serial out 4 bit shift register, but my waveforms in output have some red marks as you can see below.


I am posting my testbench too. I d be grateful if you help me with that, because i am doing a project at the university.
ENTITY Siso_Tb IS
END Siso_Tb;

ARCHITECTURE behavior OF Siso_Tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT Siso
PORT(
Sin : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
enable : IN STD_LOGIC;
Sout : OUT std_logic);
END COMPONENT;



--Inputs
signal Sin : std_logic := '0' ;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal enable : std_logic := '0';


--Outputs
signal Sout : std_logic := '0';


-- Clock period definitions
constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: Siso PORT MAP (
Sin => Sin,
clk => clk,
reset => reset,
enable => enable,
Sout => Sout);


-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

clk_enable :process
begin
enable <= '0';
wait for clk_period/2;
enable <= '1';
wait for clk_period/2;
end process;



-- Stimulus process
stim_proc: process
begin

reset <= '1';
wait for clk_period/2;
reset <= '0';
wait for clk_period/2;

Sin <= '1';
Sout <= '0';
wait for clk_period;

Sin <= '0';
Sout <='0';
wait for clk_period;

Sin <= '0';
Sout <='1';
wait for clk_period;

Sin <= '1';
Sout <='0';
wait for clk_period;

Sin <= '0';
Sout <='0';
wait for clk_period;

Sin <= '0';
Sout <='1';
wait for clk_period;
end process;


END;
Attached Images
↧

What im doing wrong using the Altera UP IP core USB

May 10, 2018, 8:08 am
$
0
0
Hey,
i am using the Altera University IP core for the USB 2.0 controller. I followed the instructions here: ftp://ftp.altera.com/up/pub/Intel_Ma...Output/USB.pdf
My FPGA is a de2-115. I created a qsys design with:
- 50Mhz clock
- on chip memory
- nios2/f cpu
- interval timer
- system id peripheral
- USB Controller
- JTAG UART
And made the pin planning in quartus, then i created a main.c file with exactly the code given in the PDF i linked. This should let me detect a usb mouse.

The USB device is recogniced (after "alt_up_usb_open_dev" i have something with the right usb base adress). But the "alt_up_usb_setup" function never returns. Inside that function i enabled the port info and i can see on the uart terminal output:


root_hub_port1 = 950095 root_hub_port2 = 960096
port1_speed = 0
port2_speed = 0
Port 1 has USB device connected, assigning address 1...

Even if no device is plugged in. I'm curious about the port speed of 0 and also the root_hub_port address is changing after each reset. Sometimes after reset a device HID is found but this is not an HID of a mouse and this HID is not always the same. Sadly there is not much documentation how to setup the USB core correctly regarding the pin planning and required qsys settings, so it is most likely that i'm missing something there. Two things i come over and was not sure if i did that right are:
1. In Quartus Pin Planner i choose 3.3V LVTTL default was 2.5V but i read in the ISP1362 manual that 3.3V is used by the USB controller.
2. I use the same clock for the usb as for the whole design (50Mhz) maybe i have to use a seperate clock with different speed?

I also tryed something more smaller. I just assign a value to the HcScratch register and try to read that value than:
Code:
    do
    {
        alt_up_usb_hc_reg_write_16(usb, 0x28, cnt);
        test_data = alt_up_usb_hc_reg_read_16(usb, 0x28);

        if(test_data!=cnt){
            printf("Error Encountered!!\n");
            printf("Write:%4X, Read:%4X\n", cnt, test_data);
            error++;
        }
        cnt++;
    } while(cnt<4);

    if(error==0)
    {
        printf("\nNo error!!\n");
    }
    else
    {
        printf("Total error : %d\n",error);
    }
But the value read in the register is not the value i wrote.

I would be grateful to any hint or advise..
↧

Quartus II- exercise. HELP !

May 10, 2018, 8:33 am
$
0
0
Hello all.
I am a beginner and I have a problem with doing exercises for classes. Unfortunately I have to give it back as soon as possible, hence my post on the forum.

"Perform a system that performs the following action:
[b·x2-a+x1]·d/c, where a=6, b=12, c=4, d=1;

x1, x2 - four-bit quadrants without a character bit entered from the switches: number x1 SW (3..0), number x2 SW (17..14).
The numbers x1, x2 are displayed on the HEX7, HEX6 displays in hexadecimal.
On the HEX5 display we display the result mark, HEX4 displays, 3, 2 display the result in decimal form, HEX0 displays, HEX1 display the fractional part in decimal form.
To implement all arithmetic operations (addition, subtraction, multiplication), use adder, subtracting in U2 code. "

I am asking for help, it is urgent!
Thank you in advance!
Regards
↧

Question about memory access pattern

May 10, 2018, 12:17 pm
$
0
0
Hi,

I have one specific questions regarding the memory access optimization in FPGA.

As we know, developers need to make sure to coalesce all memory accesses in their code. In GPU, that means all threads in a wrap to access sequential indexes of memory. I browsed the best practices of Intel FPGA with regard to this issue, but there is no specific detail on how memory access coalescing should be done? If we have single thread mode, does that mean we need to have memory indexes being sequental Temporally, as opposed to Spatially in GPU? What about ND-Range mode? in this mode we have both opportunities of optimizing memory access spatially and temporall. Can anyone elaborate on the memory manager module mechanism for handling memory accesses?

Thanks
↧
↧

Single Event Upset

May 10, 2018, 10:43 pm
$
0
0
Hello,

I am calculating Single Event Upset ratio of Cyclone V to check if it is within acceptable range. For this calculation, I need

-SEE Cross Section(cm2/bit)
-SEE Cross Section(cm2/device)

parameters. Does anybody knows how to find them? I have reached some distributors which are of no help.

Cyclone V part number is 5CGXFC7D6F31I7.

Alper
↧

Asynchronous input strobe detection

May 11, 2018, 1:07 am
$
0
0
Hello,

We are using Cyclone IV EP4CE40F23I7 and we have an implementation for an interface to a DSP (ADSP-21489, AMI Interface), which is causing us some problems with timing. The fact is that our implementation is using asynchronous edge detection through a latch, as show in picture 1. We are aware that this is probably not the best implementation but is the one that allows us to achieve the required access times and it is working stable so far.

With this solution we need a lot of timing constraints to relate the signals in both domains and be sure that we have the correct timing in our signals. We have done this combining “set_net_delays” on our sdc and some “GetMaxTimingPath” checks on a Tcl that we run after timing analysis (although there are probably best techniques to constraint signals in different clock domains). We do not always get good results in these checks, as they are not affecting routing.
We would like to simplify and improve this implementation but at the same time we are trying to keep the access times as low as they are now. So we are analyzing different possibilities:


  • Detecting input strobes with clk_sys, as shown in picture 2. To which extent is this implementation less stable or more problematic than the one shown in picture 1?
  • Keeping the implementation as picture 1, but try to constraint all the signals on the sdc, relating the signals in both clock domains, to get rid of the Tcl checks. Should this be possible? Is implementation in picture 1 against good practice recommendations?
  • Any other ideas?

    Thank you!
Attached Images
↧
Search

Error: (vsim-3033) Instantiation of 'alt_dual_boot_avmm' failed.

May 11, 2018, 1:50 am
$
0
0
Hi there

I am have a severe and persistent problem with an attempt to simulate a MAX10 Qsys (platform designer) system in Modelsim. Everytime I try to run an RTL simulation from the synthesized Qsys block, I get two errors:

Quote:
# Loading basic_spi_to_flash.altera_dual_boot# ** Error: (vsim-3033) Instantiation of 'alt_dual_boot_avmm' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /testbench_spi/dut/dual_boot_0 File: e:/projects/trunk/max10/db/ip/basic_spi_to_flash/submodules/altera_dual_boot.v Line: 41
# Searched libraries:
# E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/altera
# E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/lpm
# E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/sgate
# E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/altera_mf
# E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/altera_lnsim
# E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/fiftyfivenm
# E:/Projects/trunk/MAX10/simulation/modelsim/rtl_work
# E:/Projects/trunk/MAX10/simulation/modelsim/basic_spi_to_flash
# E:/Projects/trunk/MAX10/simulation/modelsim/basic_spi_to_flash
# Loading basic_spi_to_flash.altera_onchip_flash
# Loading basic_spi_to_flash.altera_onchip_flash_avmm_data_c ontroller
# Loading basic_spi_to_flash.altera_onchip_flash_address_ran ge_check
# Loading basic_spi_to_flash.altera_onchip_flash_convert_add ress
# ** Error: (vsim-3033) Instantiation of 'altera_onchip_flash_block' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /testbench_spi/dut/onchip_flash_0 File: e:/projects/trunk/max10/db/ip/basic_spi_to_flash/submodules/altera_onchip_flash.v Line: 305
# Searched libraries:
# E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/altera
# E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/lpm
# E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/sgate
# E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/altera_mf
# E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/altera_lnsim
# E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/fiftyfivenm
# E:/Projects/trunk/MAX10/simulation/modelsim/rtl_work
# E:/Projects/trunk/MAX10/simulation/modelsim/basic_spi_to_flash
# E:/Projects/trunk/MAX10/simulation/modelsim/basic_spi_to_flash
This is from a Qsys project containing a Clock Source, On--chip Flash (with dual boot setup), SPI to Avalon Master Bridge and 4 Pipeline Bridges. It is not a very complex system.

I have tried to manually locate the missing libraries, but including them in the .do file simply creates a different error. For some reason, Quartus is simply not generating the files that it needs to for Modelsim's use. Loading of the other libraries in the project seems to be succesful and Modelsim does not complain.

Note that I have tried this using Quartus 13.1, 16.0 and 17.1. I have attempted the simulations with Modelsim 10.2 and 10.7a (the most recent version). I have also tried this in Questa Prime. For these reasons I don't think this is a version issue.

Please help, I am desperate. Thank you in advance.
↧

Altera PLL reconfig - Simulation problem

May 11, 2018, 3:45 am
$
0
0
I am trying to simulate a PLL with a one reconfiguration module. With Quartus and ModelSim I can compile all the system (with the PLL and the reconfiguration module among others) perfectly without any errors. But when I try simulate the system completely ModelSim return this error:

# Loading work.pll_controller(funcional)
# Loading work.pll_reconfig(rtl)
# ** Warning: (vsim-3473) Component instance "pll_reconfig_inst : altera_pll_reconfig_top" is not bound.
# Time: 0 ps Iteration: 0 Instance: /vpg/PLL_RECONFIG0 File: C:/DVI_14/PLL_RECONFIG_sim/PLL_RECONFIG.vhd
# Loading altera_lnsim.altera_lnsim_components
# Loading work.pll_pxl(rtl)
# Loading sv_std.std
# Loading altera_lnsim.altera_lnsim_functions
# Loading altera_lnsim.altera_pll
# Loading altera_lnsim.dps_extra_kick
# Loading altera_lnsim.dprio_init
# Loading altera_lnsim.altera_pll_dps_lcell_comb
# Loading altera_lnsim.altera_arriav_pll
# ** Error: (vsim-3033) /build/swbuild/SJ/nightly/17.1std/590/l64/work/modelsim/eda/sim_lib/altera_lnsim.sv(24438): Instantiation of 'arriav_ffpll_reconfig' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /vpg/PLL_PXL0/pll_pxl_altera_pll_altera_pll_i_640/genblk2/genblk2/arriav_pll File: /build/swbuild/SJ/nightly/17.1std/590/l64/work/modelsim/eda/sim_lib/altera_lnsim.sv
# Searched libraries:
# C:/DVI_14/simulation/modelsim/rtl_work
# Loading work.resolution_gen(funcional)
# Loading work.vga_gen(funcional)
# Error loading design



Someone knows what can occur?

Thanks in advance.
↧
↧

A little problem in the process of using a10 soc development board

May 11, 2018, 7:23 am
$
0
0
Hello everyone,
When using the a10 soc development board for FPGA Ethernet debugging, we are using network cables to connect the network ports on the computer and the board. After connecting, it is found that the computer and network port are not connected.After troubleshooting, we found that MAX V on the board should reset the phy chip so that the phy chip can work properly.So we need to add reset logic in MAX V, but we don't know if there is a program in MAX V. If there is a program in max v, we do not know that reprogramming will not cause the soc board to work abnormally.So we want to ask if there is a program in MAX V? Does adding reset logic directly in MAX V affect the board?
Guys please suggest some solution.

Thanks in advance.
↧

Io channel conflicts with global/local memory?

May 11, 2018, 7:39 am
$
0
0
Hi everyone,
When reading data from the fpga pin using the io channel, we find that the read data cannot be passed back to the HOST from the Device (FPGA).And as shown below, the compiler will display a warning when compiling.
In the OpenCL framework, does the io channel conflict with global/local memory?
Guys please suggest some solution.

Thanks in advance.
Attached Images
↧

CPU Design

May 11, 2018, 8:44 am
$
0
0
Hi,
I want to learn about designing a cpu with rtl coding. I used to implement mips cpu. Now I want to try with other cpu. Which is the good choise to start with?
Thanks for your help
↧
Viewing all 19390 articles
Browse latest View live
Search
<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>