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EPCQ-L Obsolescence

May 13, 2018, 1:14 pm
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Hi,
Intel Altera recommends EPCQ-L to configure Intel Arria 10 device in the handbook. But in the PDN1802 says that this device family(EPCQ-L) will be removed from production.
What chips can be put into development for Intel Arria 10 device configuration?
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starting code

May 13, 2018, 3:15 pm
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Im using the Free version of
Quartus II for the Cyclone and Max for CPLD

I have a number of questions:

I am working on an old CMOS controller chip I plan on using an obsolete DIP programmer
(not programming into FPGA).
In the Quartus V9.1 software how do I start the coding process, in the software? :confused:

How do I code a Benchmark?:confused:

More questions later thank you...
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Is it possible to program MAX V on the10 soc?

May 13, 2018, 7:43 pm
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Why my self-defined QSys component does not have the same speed as on-chip memory ?

May 13, 2018, 11:09 pm
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I am having a PCIe project based on QSys that have on-chip memory component and my self-defined component and a PCIe IP core connected on Avalon bus. I just want to check out what speed between PC program to the self-defined component can reach.


Please see the attached photo, the first the avalon mm slave interface definition in my component, the second is the logic return the data to avalon mm master.


As you can see I have implemented the burst read support, but there is no much improvement after adding burst read support.

The speed of the on-chip memory component is about 2Gbps without using DMA, but my self-defined component has only about 130Mbps.

My question is,

1. How can I make a self-defined component has almost the same speed as on-chip memory component, is there a sample for reference?
2. How can I access the on-chip memory from my self-defined component?

Thank you!
Attached Images
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DDR3SDRAM IP-core, number of chip selects

May 14, 2018, 12:04 am
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hello everyone.

I am trying to create DDR3-IP core.
I want to connect two DDR3-SDRAM SODIMMs(64bits) in parallel.

each SODIMM has two chip selects pins.
so the case needs four chip selects.

I try to do so in QuartusPrime 15.1.
but I only can select two chip selects.( see attached file )

I think old version of QuartusII could set bigger number, because in that time I set the number directory.

how can I set lager number? or can't I do that?
Attached Images
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Good editor for OpenCL in linux (.cl files)

May 14, 2018, 12:09 am
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I have tried installing the opencl extensions for visual code and eclipse. They do not work. Any suggestions from your side?
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Standart quartz oscillator

May 14, 2018, 12:27 am
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i connect standart oscillator ALTUFM_OSC osc( .oscena(1'b1), .osc(clk))
i count 6 000 000 by counter.
Code:
begin
counter = counter+ 1'b1;
if(counter == const_data)
 begin
 signal = ~signal;
 counter = 25'b0;
end
LED blinks once per second.
Is it means, that frequency of quartz oscillator is 6MHz (instead of 50MHz)?
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Why my self-defined QSys component does not have the same speed as on-chip memory ?

May 14, 2018, 12:38 am
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I am having a PCIe project based on QSys that have on-chip memory component and my self-defined component and a PCIe IP core connected on Avalon bus. I just want to check out what speed between PC program to the self-defined component can reach.


Please see the attached photo, the first the avalon mm slave interface definition in my component, the second is the logic return the data to avalon mm master.


As you can see I have implemented the burst read support, but there is no much improvement after adding burst read support.

The speed of the on-chip memory component is about 2Gbps without using DMA, but my self-defined component has only about 130Mbps.

My question is,

1. How can I make a self-defined component has almost the same speed as on-chip memory component, is there a sample for reference?
2. How can I access the on-chip memory from my self-defined component?

Thank you!
Attached Images
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How to find problem in design after compiliation / fitter failure

May 14, 2018, 1:43 am
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Hello everyone.

I have created a project that according to the HTML report has the following estimates:

Kernel Name ALUTs FFs RAMs DSPs
Total 61485 (56%) 72984 (33%) 322 (63%) 94 (84%)
Available 109572 219144 514 112

In the file top.fit.rpt I can see the following summary after compilation:

Code:
; Fitter Summary                                                                    ;
+---------------------------------+-------------------------------------------------+
; Fitter Status                  ; Failed - Wed Apr 25 23:51:32 2018              ;
; Quartus Prime Version          ; 17.1.0 Build 590 10/25/2017 SJ Standard Edition ;
; Revision Name                  ; top                                            ;
; Top-level Entity Name          ; top                                            ;
; Family                          ; Cyclone V                                      ;
; Device                          ; 5CSEMA5F31C6                                    ;
; Timing Models                  ; Final                                          ;
; Logic utilization (in ALMs)    ; 32,070 / 32,070 ( 100 % )                      ;
; Total registers                ; 65218                                          ;
; Total pins                      ; 115 / 457 ( 25 % )                              ;
; Total virtual pins              ; 0                                              ;
; Total block memory bits        ; 1,389,980 / 4,065,280 ( 34 % )                  ;
; Total RAM Blocks                ; 0 / 397 ( 0 % )                                ;
; Total DSP Blocks                ; 87 / 87 ( 100 % )                              ;
; Total HSSI RX PCSs              ; 0                                              ;
; Total HSSI PMA RX Deserializers ; 0                                              ;
; Total HSSI TX PCSs              ; 0                                              ;
; Total HSSI PMA TX Serializers  ; 0                                              ;
; Total PLLs                      ; 2 / 6 ( 33 % )                                  ;
; Total DLLs                      ; 1 / 4 ( 25 % )                                  ;
+---------------------------------+-------------------------------------------------+
However, the process fails with the following message in the same file:

Code:
Error (170012): Fitter requires 3213 LABs to implement the design, but the device contains only 3207 LABs
I can't find the reason for this and in contrast to the HTML report there is no link to which lines of the source code are causing what resource usage. Is there any way to get a more accurate HTML report based on the actual compilation to find the reason for the increased resource usage? It seems there is quite a discrepancy between the estimate and the actual usage so I wonder how this can be traced / understood and fixed in the code. Any ideas are much appreciated.

Board: Cyclone V, 5CSXFC6D6F31C8ES, de1soc:de1soc_sharedonly
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UP installer lags behind Quartus version

May 14, 2018, 2:51 am
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Hi!

Current Quartus version just changed to 18.0. UP installer is still only available in version 16.1. No updates in 2017. Any idea whe we will see an update?

The tools and tutorials provided by the University Program are extremely valuable for the courses we give here at the university. In fact they are a major reason why Altera/intel is used instead of Xilinx. Since these materials begin to date their value diminishes of course.

Thanks,
Markus
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Synchronization of data, control and clock inputs in QuartusII

May 14, 2018, 3:39 am
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Hey everyone,

i am getting a data(4 Bit), a control(1 Bit) and a clock signal from the Cyclone V pins which are driven by extern sources.
These signals are misaligned and i want to align the control and the data signals to the extern clock signal in my FPGA design.

Are there any Altera/QuartusII provided IP-Cores available to this task? What is the best method to align them?

The deskew isn't static, so timing constrains are probably not the right solution.
I am using Cyclone V and QuartusII 2017.

Every help is very appreciated, thanks in advance.

Best regards
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Don't work DDIO input registers in Arria 10

May 14, 2018, 5:21 am
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Hello.
I try migrat a desig from Cyclone V to Arria 10 with DDR inpu. I have 4 data line and 1 clock line with data rate 444.5 Mbit/s and clock rate 222.25 MHz. In Cyclone I used the ALTDDIO_IN megafuncton (I instantiated it without Megawithard) and Quartus 13.1.
Now I use Arria 10 GX and Quartus Prime Pro 17.1. When I sinthesize my code Quartus dont use DDIO registers and TimeQuest report a slacks. But in Cyclone V this design use a DDIO registers in pins block.
Also I try compilate the design with altlvds_rx core and with twentynm_ddio_in (it used in core Altera GPIO) but everething got same result: quartus dont use unput DDIO registers and inplement DDR input on LEs. Also I try use FastInpitRegisters assignmet and constrains from Altera GPIO manual, but I cant implement logic with Input DDIO registers.

Please help me use dedicaes input DDIO registers.
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Trouble in Flashing to eMMC using USB blaster

May 14, 2018, 7:11 am
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Hi All,

We are trying flash the binaries to eMMC using USB-Blaster II

When I executed the below command it ends up with errors:
./flash_programmer.py --operation=epv --address=0x00000000 --size=0x00100000 --file=<path>/uboot_w_dtb-mkpimage.bin
(refered as in link https://rocketboards.org/foswiki/Doc...7938d664df12c1)

Debug messages:
Launching debug server [0%]
[target] Starting debug server
[target] Waiting for debug server to start accepting connections
[target] Debug server started successfully
[target]
Launching debug server [100%]
[target] ERROR failed to connect to RDDI DAP target
[target] RDDI Error Code 4107 : Failed to load JTAG client library "libjtag_client.so"
[target] RDDI CFG = /tmp/ds5_1842063425346091758.txt
[target] Debug server shutdown application
[target] Debug server shutdown attempted
[target] Done
WARNING(DTS255): Failed to power down DAP
ERROR(TAD290-DTS77-DTS1-NAL57):
! Failed to connect to platform TCP:localhost
! Unable to connect to TCP:localhost
! Unable to connect to device DAP
! No connection to target.
INFO : WARNING(DTS255): Failed to power down DAP
ERROR(TAD290-DTS77-DTS1-NAL57):
! Failed to connect to platform TCP:localhost
! Unable to connect to TCP:localhost
! Unable to connect to device DAP
! No connection to target.

ERROR: Launching debug server [0%]
[target] Starting debug server
[target] Waiting for debug server to start accepting connections
[target] Debug server started successfully
[target]
Launching debug server [100%]
[target] ERROR failed to connect to RDDI DAP target
[target] RDDI Error Code 4107 : Failed to load JTAG client library "libjtag_client.so"
[target] RDDI CFG = /tmp/ds5_1842063425346091758.txt
[target] Debug server shutdown application
[target] Debug server shutdown attempted
[target] Done

What could have caused this error? Has anyone faced the same problem before??

Thank you.
Regards,
Ambika
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What is the lowest power FPGA board/card available in the market?

May 14, 2018, 8:07 am
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Hello,
I'm working on a project in which an FPGA should be used in a mobile phone, so the FPGA has to draw as few power as possible. so i have to find a very low power FPGA to work on it.
What is actually the most low power FPGA known?

Thanks and best regards
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drive the input pins during the power-up/down sequence

May 14, 2018, 9:42 am
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Hi,
Can I set the output of the external, peripheral chips(connected to the FPGA Arria10) in the in the VCCIO-GND voltage range during the power-up/down sequence for LVDS Banks?
Can I set the output of the external, peripheral chips(connected to the FPGA Arria10) in the in the VCCIO-GND voltage range during the power-up/down sequence for 3V Banks?
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EP3C40F780C6 PCIe implementation

May 14, 2018, 9:55 am
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Hi,

I would like to know the recommended I/O voltage for PCIe implementation in EP3C40F780C6 FPGA.
Thanks.

Regards,
Sathya
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MSEL driving

May 14, 2018, 10:41 am
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Hi,
On page 246 Arria10 Handbook says: "To select a configuration scheme, hardwire the MSEL pins to VCCPGM or GND without
pull-up or pull-down resistors."
On page 247 Arria10 Handbook says: "Do not drive the MSEL pins with a microprocessor or another device."

Why not?
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quartus with arria10 dev board supports all arria10 devices?

May 14, 2018, 11:52 am
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Hi - I'm doing a design with a smaller Arria10 device, the Gx320.

If I buy the Altera Arria10 dev board with a larger device, is Quartus Prime Pro limited to the device on the dev board or is it good for all Arria 10 devices?

Thanks
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FPGA Power Measurement

May 14, 2018, 12:46 pm
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Hello all,

FPGA power measurement is very important to estimate the efficiency of the applied algorithm using OpenCL (or an HDL),
nevertheless i couldn't find a way to measure the power needed by the FPGA in the DE10-Nano board, especially at run time.
is there some way at least to estimate the power consumption of a compiled OpenCL Kernel,
is it feasible to use the amp-meter on the FPGA board?

Thanks in advance
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writing and reading the same pipe in one kernel

May 14, 2018, 3:43 pm
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Hi
I want to write and read the same pipe in one kernel like this:

channel float c0 __attribute__((depth(2)));
__kernel void testkernel() {

for(int i = 0; i < n; i ++){
page_ranks[i] = read_channel_intel(c0); //read from the channel
}

for(int i = 0; i < n; i ++){
//do some computation of the page_rank[i] and generage new_rank
write_channel_intel(c0, new_rank); //write new_rank to this pipe

}

}
and this kernel is being run in multiple iterations, each time it will read from last iteration's result and compute new rank and use the new rank as the new input for the next iteration.
When I compile this, I get the error of "Compiler Error: Multiple writes to channel c0", this is the only line I got in the log.
Any suggestions on how to deal with this case using pipe or how to resolve this bug?
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