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create_generated_clock on multiple signals

May 14, 2018, 4:00 pm
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I have a large array of DDR outputs that are being used as clocks. I'm following an example from AN433.pdf, though the document describes the constraint for only a single clock. How can I do this multiple times without typing out every single element? For example, is there a way to simplify this:

create_generated_clock -name output_clock_0 -source \[get_pins DDR|ddio_outa[0]|muxsel] [get_ports clk_out]
create_generated_clock -name output_clock_1 -source \ [get_pins DDR|ddio_outa[1]|muxsel] [get_ports clk_out]
create_generated_clock -name output_clock_2 -source \ [get_pins DDR|ddio_outa[2]|muxsel] [get_ports clk_out]
...
create_generated_clock -name output_clock_59 -source \ [get_pins DDR|ddio_outa[59]|muxsel] [get_ports clk_out]


It seems like there should be a something like a for loop like this (excuse the psuedo-code):

for i in xrange(60):
create_generated_clock -name output_clock_{i} -source \ [get_pins DDR|ddio_outa[i]|muxsel] [get_ports clk_out]
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what problem with SDK for OPenCL v17.1

May 14, 2018, 8:49 pm
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Hi all!
I'm trying run opencl example hello_world on quartus v17.1.
the compiler guider document wrote that compiler time may some hours. but i run two days, still don't have result.
what is the matter with my object?

Thanks for your help.
Attached Images
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How to obtain a valid license of FPGA SDK for OpenCL

May 14, 2018, 11:26 pm
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Hi all,
I dont know how to obtain a valid SDK for OpenCL License of v16 or v17?
please help...
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OpenCL kernel takes more than 36 hours to compile on Arria 10

May 15, 2018, 2:44 am
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Dear community,

Before the weekend I started the compilation of my OpenCL kernel using the Intel SDK for OpenCL for the Arria 10 FPGA board. I had compiled an unoptimized version of this kernel before, and that took about 4 hours of compiling and synthesis. When I checked the status of the compilation yesterday (more than 36 hours after starting), I saw it was still busy, and the quartus_sh_compile.log (see attachment) seemed to be stuck in the middle of a line of output. I read on this forum that for the Arria 10 it should take at most around 12 hours to synthesize a large design, so this made me think my compilation was just hanging.

The compilation used about 28GB of the 64GB available RAM of my build machine, and when it was stuck there was only 1 core being used by the `quartus_syn top -c top_synth` process. If it is of any help, the emulation and verification of the kernel was fine, and gave the same results as the (compilable) unoptimized version of the kernel. The main optimizations are the use of local memory and loop unrolling, and I also changed from a task kernel to ND-Range kernel type. The resource usage is significantly more than the unoptimized version, but still estimated to be within the available resources on the Arria 10 (as you can see in the Optimization Report attached as "my_kernel.txt").

I don't know what I can do to further debug this as there is no output, so I hope there is someone on this forum that maybe experienced this before, and could help me out.

Cheers!
Attached Files
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Embedded JAM byte-code player failure with Quartus 17

May 15, 2018, 5:50 am
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Hi all

I implemented the Jam STAPL ByteCode Player (revision 2.2) on an embedded platform in order to program/configure a MAX10 FPGA via JTAG directly from an embedded processor.

This was working well and the sequence of events to update the MAX 10 was:
- Compile new FPGA image in Quartus v15 or v16.
- Convert *.pof to *.jbc using Quartus Programmer.
- Compile *.jbc data as part of embedded software image.
- Run embedded application, which then updates the FPGA via the JTAG port.

With Quartus v17 I find that the embedded JAM byte-code Player fails with an exit code 10: JBIC_INTERNAL_ERROR.

What I have found is the following:
- The v17 *.jbc (generated from the *.pof) triggers a "configuring SRAM device(s)..." step which was not seen during programming before.
- On inspecting the *.jam format for quartus v16 and v17 I saw that the "ALG_VERSION" has incremented from 67 to 68. (JAM version remains 2.0)
- I can compile my FPGA image with Quartus v17 and then use the quartus_cpf.exe utility from Quartus 16 to generate the *.jbc and achieve success. (Hence I assume algorithm 67 or 68 is used within the quartus_cpf.exe utility...)

My questions:
- What changed between JAM generation algorithm 67 and 68 and why?
- Is this a known issue that the embedded STAPL bytecode player is unable to program pof jbc files generated with algorithm 68? (or is this an issue with my implementation of the jbc player)

I can obviously use the workaround as described, but would appreciate any more information on this to ensure that I do not run into incompatibilities in the future.
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Compile error whilel using Quartus Prime

May 15, 2018, 7:49 am
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I am getting the following compile errors while compiling a project in quartus prime, as follows:
Error (275029): Incorrect connector style at port "dataa[7..0]" for symbol "inst" of type mult

Error (275029): Incorrect connector style at port "datab[7..0]" for symbol "inst" of type mult



Error (12153): Can't elaborate top-level user hierarchy

I tried changing to bus line, but it dint work. I also tried using a diagonal bus tool while drawing. That dint work either.

Please help.
Attached Images
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Bug in altera_16550_uart_init.c (altera_16550_uart_init function)

May 15, 2018, 8:06 am
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Hello,

I had a problem with interrupt handling with the 16550 core.
Presumably a programming error in the C code of the component:
The uart did not process receive interrupts properly from the start.
What follows is an exact copy of the nios code for the uart:

altera_16550_uart_init.c line 439:
/* enable interrupts at the device */
regs = IORD_ALTERA_16550_UART_IER(sp->base);
regs |= ALTERA_16550_UART_IER_ERBFI_MSK | ALTERA_16550_UART_IER_ETBEI_MSK;
IOWR_ALTERA_16550_UART_IER(base, sp->ctrl);

}

Should be:

altera_16550_uart_init.c line 439:
/* enable interrupts at the device */
sp->ctrl = IORD_ALTERA_16550_UART_IER(sp->base);
sp->ctrl |= ALTERA_16550_UART_IER_ERBFI_MSK | ALTERA_16550_UART_IER_ETBEI_MSK;
IOWR_ALTERA_16550_UART_IER(base, sp->ctrl);

}

=> reading the interrupt enable register, modifying the read contents and then writing the result back using a different value does not make sense.

Best Regards,
Johi.
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startix V hard ip pcie pld_clk_inuse is low

May 15, 2018, 8:20 am
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Good afternoon colleague.
Still trying to start hard ip core pcie. I figured out that the signal pld_clk_inuse is in a low state (0) and reset_status is in constan 1.
Maybe someone had such an experience, where to start looking for a problem?
Thank you in advance.
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Problem in configuring Cyclone V GT development kit pins for 1.2V voltage level

May 15, 2018, 9:44 am
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I have a Cyclone V GT development kit to do some testing, and I need to use the pins of the HSMB connector with voltage level of 1.2V as simple I/O. But when I connect pins 5-6 from the J17 connector, my design does not work. Do I need any additional configuration to be made?
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channel deadlock

May 15, 2018, 10:25 am
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The below source code is used in opencl programming guide. It is told that without using "mem_fence(CLK_CHANNEL_MEM_FENCE)", the consumer module might end up with deadlock.

1) Consider a case where producer has written in channel c0 first and consumer has read from channel c1. Consumer is currently reading from empty channel. It would stall for couple of cycles but why would there be a DEADLOCK?

2) Cant producer write in channel c0 and c1 in parallel?


__kernel void producer (__global const uint * src,
const uint iterations)
{
for (int i = 0; i < iterations; i++)
{
write_channel_intel(c0, src[2*i]);
write_channel_intel(c1, src[2*i+1]);
}
}
__kernel void consumer (__global uint * dst,
const uint iterations)
{
for (int i = 0; i < iterations; i++)
{
/*During compilation, the AOC might reorder the way the consumer
kernel
writes to memory to optimize memory access. Therefore, c1 might be
read
before c0, which is the reverse of what appears in code.*/
dst[2*i+1] = read_channel_intel(c0);
dst[2*i] = read_channel_intel(c1);
}
}
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DE0-Nano-SoC Custom Design Preloader to Use With Alter Monitor Program

May 16, 2018, 2:45 am
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Hello,

I am trying to export HPS I2C controller pins to the GPIO header on the DE0-Nano-Soc board but I am having some trouble with that.

Things I have done and their results are as follows:


1. I modified the QSYS file and exported the I2C0 signals to FPGA. Then connected the these I2C signals to the user I/Os.

2. Compiled the design successfully

3. Generated and compiled preloader for the new qsys design following the instructions:


https://rocketboards.org/foswiki/Doc...RD141Preloader


4. I found that the preloader file used by the Monitor Program (IDE) is of 'srec' format while the SoC EDS tool has generated a binary file. So I converted the binary to srec using 'srec_cat' program and gave an offset of '0xffff0000' as I saw in the original srec file.


5. I replaced the sof, socinfo and srec files used by the monitor program with the newly generated ones.


6. When I download the program to the board the sof file is successfully downloaded but the hps is not configured correctly and error is returned as:


">>Downloading preloader......>>Setting vector base address register to: 0xffff0000
Timed out while waiting for preloader to finish
Preloader failed to run. HPS components may not have been configured.
Possible causes for the failure:
1. Linux SD card is inserted and Linux is running.
2. FPGA-side components are accessing HPS memory."

(SD card is plugged out so definitely no Linux is running)



7. If I use the old preloader file (one that came pre-compiled with the altera monitor program) with the new sof file then I don't get this error but the user I/o pins are at floating voltage level around 2v.


8. I notice one difference in the terminal when I run original preloader and new preloader as:


original preloader:
>>CPU0 halted at 0x2fa4.
>>Resetting HPS.
>>Downloading preloader.....
>>Program loaded. PC set to program entry (0xFFFF0000)
>>Setting vector base address register to: 0xffff0000
>>Running preloader..



new preloader:
>>CPU0 halted at 0x2fa8.
>>Resetting HPS.
>>Downloading preloader......>>Setting vector base address register to: 0xffff0000
Timed out while waiting for preloader to finish


I have added the colors here to the text to make the red line prominent which is 'Program loaded' that is only seen with the old preloader but not with the new preloader.


9. I opened up both the preloader files in text editor and saw the difference that beginning line for old preloader is 'S315' while for the new preloader is 'S325'. I am attaching both the preloader files to this email.

Can anyone share how to make a preloader to run with altera monitor program?

Thank you.

Best regards,
Shaji Baig

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Thread 284 #1 stopped on signal 20 : Cyclone V development kit, OpenCL on ARM-Linux

May 16, 2018, 9:01 am
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Hello !
This message appears in debugger DS-5 in progress of stepping through OpenCL function "clCreateProgramWithBinary()" with .aocx-file from Linux-application.
If I press F8 7 times in DS-5, then all these "strange" stop-situations is passed and application runs successful.
Is any method to disable this "signal 20" for getting good working debugger-independent program ?
I use "pthread_sigmask()" with SIG_BLOCK to signal 20 (SIGTSTP, keyboard stop, Ctrl-Z), calls "sigignore(20)" -- test call of "raise(20)" is good, and original call of "clCreateProgramWithBinary()" leaved bad.
Also I try to hold this signal with my callback function through "sigaction()" -- it is not called, only DS-5 see this signal.
Anybody see similar problem ?
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Question about HPS simulation

May 16, 2018, 11:17 am
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Hi,

I'm trying to run the BFM Simulation Example given in the web site: (https://www.altera.com/support/suppo...s-axi-bfm.html.) However, I got the following error saying that export_tramp.so cannot be compiled. What is this file? Why does vsim need to invoke gcc? Do I need to install 32-bit glib? Thanks!


eval vsim -t ps $ELAB_OPTIONS -L work -L work_lib -L altera_common_sv_packagess -L border -L id_pad -L hps_io -L fpga_interfaces -L rst_controller -L mm_intercconnect_0 -L hps_0 -L demo_axi_memory_0 -L HPS_h2f_axi_sim_inst_reset_bfm -L HPS__h2f_axi_sim_inst_clk_bfm -L HPS_h2f_axi_sim_inst $TOP_LEVEL_NAME
# vsim -t ps -L work -L work_lib -L altera_common_sv_packagess -L border -L id_pad -L hps_io -L fpga_interfaces -L rst_controller -L mm_intercconnect_0 -L hps_0 -L demo_axi_memory_0 -L HPS_h2f_axi_sim_inst_reset_bfm -L HPS__h2f_axi_sim_inst_clk_bfm -L HPS_h2f_axi_sim_inst HPS_h2f_axi_sim_tb
# Start time: 20:54:15 on May 15,2018
# ** Warning: ** Warning: (vsim-7032) The 32-bit glibc RPM does not appear to be installed on this machine. Calls to gcc may fail.
#
# ** Warning: ** Warning: (vsim-7032) The 32-bit glibc RPM does not appear to be installed on this machine. Calls to gcc may fail.
#
# ** Fatal: ** Error: (vsim-3827) Could not compile 'export_tramp.so': cmd = '/bin/gcc -shared -fPIC -m32 -g -I. -I"/home/qiqiu/intelFPGA/17.1/modelsim_ae/include" -I"/home/qiqiu/intelFPGA/17.1/modelsim_ae/../oem/include" -o "/tmp/qiqiu@lcs-vc-linux-01_dpi_29610/linuxpe_gcc-4.8.5/export_tramp.so" "/tmp/qiqiu@lcs-vc-linux-01_dpi_29610/linuxpe_gcc-4.8.5/export_tramp.S"'
# (vsim-50) A call to system(/bin/gcc -shared -fPIC -m32 -g -I. -I"/home/qiqiu/intelFPGA/17.1/modelsim_ae/include" -I"/home/qiqiu/intelFPGA/17.1/modelsim_ae/../oem/include" -o "/tmp/qiqiu@lcs-vc-linux-01_dpi_29610/linuxpe_gcc-4.8.5/export_tramp.so" "/tmp/qiqiu@lcs-vc-linux-01_dpi_29610/linuxpe_gcc-4.8.5/export_tramp.S" >'/tmp/questatmp.0CZnVC' 2>&1) returned error code '1'.
# The logfile contains the following messages:
# /bin/ld: cannot find crti.o: No such file or directory
# /bin/ld: cannot find -lc
# /bin/ld: cannot find crtn.o: No such file or directory
# collect2: error: ld returned 1 exit status
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HPS BFM simulation error

May 16, 2018, 11:24 am
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Hi,

When I tried to run the BFM Simulation Example from (https://www.altera.com/support/suppo...s-axi-bfm.html), I got an error saying that cannot compile export_tramp.so. The error message is as the following. What is the file "export_tramp.so"? I don't see it in any of the Verilog file or simulation script. Why the vsim invoke gcc? Based on the error message, should I install a 32-bit glibc? Thanks!

*************************************************

eval vsim -t ps $ELAB_OPTIONS -L work -L work_lib -L altera_common_sv_packagess -L border -L id_pad -L hps_io -L fpga_interfaces -L rst_controller -L mm_intercconnect_0 -L hps_0 -L demo_axi_memory_0 -L HPS_h2f_axi_sim_inst_reset_bfm -L HPS__h2f_axi_sim_inst_clk_bfm -L HPS_h2f_axi_sim_inst $TOP_LEVEL_NAME
# vsim -t ps -L work -L work_lib -L altera_common_sv_packagess -L border -L id_pad -L hps_io -L fpga_interfaces -L rst_controller -L mm_intercconnect_0 -L hps_0 -L demo_axi_memory_0 -L HPS_h2f_axi_sim_inst_reset_bfm -L HPS__h2f_axi_sim_inst_clk_bfm -L HPS_h2f_axi_sim_inst HPS_h2f_axi_sim_tb
# Start time: 20:54:15 on May 15,2018
# ** Warning: ** Warning: (vsim-7032) The 32-bit glibc RPM does not appear to be installed on this machine. Calls to gcc may fail.
#
# ** Warning: ** Warning: (vsim-7032) The 32-bit glibc RPM does not appear to be installed on this machine. Calls to gcc may fail.
#
# ** Fatal: ** Error: (vsim-3827) Could not compile 'export_tramp.so': cmd = '/bin/gcc -shared -fPIC -m32 -g -I. -I"/home/qiqiu/intelFPGA/17.1/modelsim_ae/include" -I"/home/qiqiu/intelFPGA/17.1/modelsim_ae/../oem/include" -o "/tmp/qiqiu@lcs-vc-linux-01_dpi_29610/linuxpe_gcc-4.8.5/export_tramp.so" "/tmp/qiqiu@lcs-vc-linux-01_dpi_29610/linuxpe_gcc-4.8.5/export_tramp.S"'
# (vsim-50) A call to system(/bin/gcc -shared -fPIC -m32 -g -I. -I"/home/qiqiu/intelFPGA/17.1/modelsim_ae/include" -I"/home/qiqiu/intelFPGA/17.1/modelsim_ae/../oem/include" -o "/tmp/qiqiu@lcs-vc-linux-01_dpi_29610/linuxpe_gcc-4.8.5/export_tramp.so" "/tmp/qiqiu@lcs-vc-linux-01_dpi_29610/linuxpe_gcc-4.8.5/export_tramp.S" >'/tmp/questatmp.0CZnVC' 2>&1) returned error code '1'.
# The logfile contains the following messages:
# /bin/ld: cannot find crti.o: No such file or directory
# /bin/ld: cannot find -lc
# /bin/ld: cannot find crtn.o: No such file or directory
# collect2: error: ld returned 1 exit status
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Can not program MAX7000

May 16, 2018, 3:01 pm
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I can not program my MAX7000.

I fell back to Quartus 13.0sp1 in order to create the POF. I can not get that POF into the part.

The part I'm using is the EPM7064AETC44-10N

The programmer identifies the part as a EPM7064AE. I have tried creating POFs for the EPM7064AETA and EPM7064AETC.

In both cases the programmer aborts because the part found on the JTAG chain does not match the part in the POF.

What am I doing wrong?

:confused:
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Arria 10 PCIe Avalon-MM DMA Reference Design: Read/Write Timeout

May 16, 2018, 4:42 pm
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Hi guys,

I tried searching through the forum for this and found some posts on it but no solution to the issue. I am currently in possession of a Nallatech 385a PCIe card with an Arria 10 on it. I am running this on CentOS 7 and using Quartus Prime version 17.1. What I've done with the Avalon-MM DMA reference design ( https://www.altera.com/en_US/pdfs/li...e/an/an690.pdf ) is change the device and the pin assignments. The reference design archive package I am using is "hip_a10gx_g3_x8_avmm_dma256_1602_PS.qar". I am able to generate the HDL, fully compile, and program the .jic file into flash and restart the PC so the design saves and re-enumerates the PCIe bus properly. I am also able to make the test throughput code, install the driver, and run the program. However, the read/write test is timing out. I am able to see the device in lspci and output its details. Attached are screenshots of Quartus and the terminal output is below. Any and all help is greatly appreciated!

Code:
[arclab@p56-138 ~]$ cd Downloads/
[arclab@p56-138 Downloads]$ cd avmm_dma_linux/
[arclab@p56-138 avmm_dma_linux]$ su
Password:
[root@p56-138 avmm_dma_linux]# make
make -C /lib/modules/3.10.0-862.2.3.el7.x86_64/build M=/home/arclab/Downloads/avmm_dma_linux
make[1]: Entering directory `/usr/src/kernels/3.10.0-862.2.3.el7.x86_64'
  Building modules, stage 2.
  MODPOST 1 modules
make[1]: Leaving directory `/usr/src/kernels/3.10.0-862.2.3.el7.x86_64'
[root@p56-138 avmm_dma_linux]# ./install
rm -rf *.o *~ core .depend .*.cmd *.ko *.mod.c .tmp_versions *.symvers *.order
make -C /lib/modules/3.10.0-862.2.3.el7.x86_64/build M=/home/arclab/Downloads/avmm_dma_linux
make[1]: Entering directory `/usr/src/kernels/3.10.0-862.2.3.el7.x86_64'
  LD      /home/arclab/Downloads/avmm_dma_linux/built-in.o
  CC [M]  /home/arclab/Downloads/avmm_dma_linux/altera_dma.o
/home/arclab/Downloads/avmm_dma_linux/altera_dma.c: In function ‘init_rp_mem’:
/home/arclab/Downloads/avmm_dma_linux/altera_dma.c:272:9: warning: unused variable ‘increment_value’ [-Wunused-variable]
    u32 increment_value = 0;
        ^
/home/arclab/Downloads/avmm_dma_linux/altera_dma.c: In function ‘rp_ep_compare’:
/home/arclab/Downloads/avmm_dma_linux/altera_dma.c:287:9: warning: unused variable ‘count’ [-Wunused-variable]
    u32 count = 1;
        ^
/home/arclab/Downloads/avmm_dma_linux/altera_dma.c:286:12: warning: unused variable ‘rp_tmp’ [-Wunused-variable]
    u32 j, rp_tmp, ep_tmp;
            ^
/home/arclab/Downloads/avmm_dma_linux/altera_dma.c: In function ‘dma_test’:
/home/arclab/Downloads/avmm_dma_linux/altera_dma.c:362:13: warning: unused variable ‘ep_tmp’ [-Wunused-variable]
 u32 rp_tmp, ep_tmp;
            ^
/home/arclab/Downloads/avmm_dma_linux/altera_dma.c:362:5: warning: unused variable ‘rp_tmp’ [-Wunused-variable]
 u32 rp_tmp, ep_tmp;
    ^
/home/arclab/Downloads/avmm_dma_linux/altera_dma.c:361:12: warning: unused variable ‘j’ [-Wunused-variable]
    int i, j;
            ^
/home/arclab/Downloads/avmm_dma_linux/altera_dma.c:360:63: warning: unused variable ‘simul_write_count’ [-Wunused-variable]
    int loop_count = 0, num_loop_count = 1, simul_read_count, simul_write_count;
                                                              ^
/home/arclab/Downloads/avmm_dma_linux/altera_dma.c:360:45: warning: unused variable ‘simul_read_count’ [-Wunused-variable]
    int loop_count = 0, num_loop_count = 1, simul_read_count, simul_write_count;
                                            ^
/home/arclab/Downloads/avmm_dma_linux/altera_dma.c:360:25: warning: unused variable ‘num_loop_count’ [-Wunused-variable]
    int loop_count = 0, num_loop_count = 1, simul_read_count, simul_write_count;
                        ^
/home/arclab/Downloads/avmm_dma_linux/altera_dma.c:360:9: warning: unused variable ‘loop_count’ [-Wunused-variable]
    int loop_count = 0, num_loop_count = 1, simul_read_count, simul_write_count;
        ^
In file included from /home/arclab/Downloads/avmm_dma_linux/altera_dma.c:15:0:
/home/arclab/Downloads/avmm_dma_linux/altera_dma.c: At top level:
/home/arclab/Downloads/avmm_dma_linux/altera_dma.h:171:12: warning: ‘rp_compare’ declared ‘static’ but never defined [-Wunused-function]
 static int rp_compare(u8 *virt_addr1, u8 *virt_addr2, u32 num_dwords);
            ^
/home/arclab/Downloads/avmm_dma_linux/altera_dma.c: In function ‘rp_ep_compare.isra.5’:
/home/arclab/Downloads/avmm_dma_linux/altera_dma.c:313:14: warning: ‘ep_tmp’ may be used uninitialized in this function [-Wmaybe-uninitialized]
        printk(KERN_DEBUG "ep_tmp = %08x\n", ep_tmp);
              ^
  Building modules, stage 2.
  MODPOST 1 modules
  CC      /home/arclab/Downloads/avmm_dma_linux/altera_dma.mod.o
  LD [M]  /home/arclab/Downloads/avmm_dma_linux/altera_dma.ko
make[1]: Leaving directory `/usr/src/kernels/3.10.0-862.2.3.el7.x86_64'
[root@p56-138 avmm_dma_linux]#





**********************************************
** ALTERA AVMM DMA driver                  **
** version 2.02                              **
** 1) start DMA                            **
** 2) enable/disable read dma              **
** 3) enable/disable write dma              **
** 4) enable/disable simul dma              **
** 5) set num dwords (256 - 2048)          **
** 6) set num descriptors (1 - 128)        **
** 8) loop dma                              **
** 10) exit                                **
**********************************************
Run Read                ? 1
Run Write              ? 1
Run Simultaneous        ? 1
Read Passed            ? 0
Write Passed            ? 0
Simultaneous Passed    ? 0
Read EPLast timeout    ? 1
Write EPLast timeout    ? 1
Number of Dwords/Desc  : 512
Number of Descriptors  : 128
Length of transfer      : 256 KB
Rootport address offset : 0
Read Time              : 0 s and 249767 us
Read Throughput        : 0.000978 GB/S
Write Time              : 0 s and 216415 us
Write Throughput        : 0.001128 GB/S
Simultaneous Time      : 0 s and 270368 us
Simultaneous Throughput : 0.001807 GB/S
#





[arclab@p56-138 ~]$ sudo lspci -s 01:00.0 -vvv
[sudo] password for arclab:
01:00.0 Non-VGA unclassified device: Altera Corporation Device e003 (rev 01)
    Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
    Latency: 0, Cache Line Size: 64 bytes
    Interrupt: pin A routed to IRQ 33
    Region 0: Memory at f0120000 (64-bit, prefetchable) [size=512]
    Region 4: Memory at f0100000 (64-bit, prefetchable) [size=128K]
    Capabilities: [50] MSI: Enable+ Count=1/4 Maskable- 64bit+
        Address: 00000000fee003d8  Data: 0000
    Capabilities: [78] Power Management version 3
        Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
        Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [80] Express (v2) Endpoint, MSI 00
        DevCap:    MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
            ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 75.000W
        DevCtl:    Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
            RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+
            MaxPayload 256 bytes, MaxReadReq 512 bytes
        DevSta:    CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
        LnkCap:    Port #1, Speed 8GT/s, Width x8, ASPM not supported, Exit Latency L0s <4us, L1 <1us
            ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
        LnkCtl:    ASPM Disabled; RCB 64 bytes Disabled- CommClk+
            ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
        LnkSta:    Speed 8GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
        DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR-, OBFF Not Supported
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
        LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
            Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
            Compliance De-emphasis: -6dB
        LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+, EqualizationPhase1+
            EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest-
    Capabilities: [100 v1] Virtual Channel
        Caps:    LPEVC=0 RefClk=100ns PATEntryBits=1
        Arb:    Fixed- WRR32- WRR64- WRR128-
        Ctrl:    ArbSelect=Fixed
        Status:    InProgress-
        VC0:    Caps:    PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
            Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
            Ctrl:    Enable+ ID=0 ArbSelect=Fixed TC/VC=01
            Status:    NegoPending- InProgress-
    Capabilities: [200 v1] Vendor Specific Information: ID=1172 Rev=0 Len=044 <?>
    Capabilities: [300 v1] #19
    Capabilities: [800 v1] Advanced Error Reporting
        UESta:    DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
        UEMsk:    DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
        UESvrt:    DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
        CESta:    RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
        CEMsk:    RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
        AERCap:    First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
    Kernel driver in use: Altera DMA

[arclab@p56-138 ~]$





[arclab@p56-138 ~]$ ls /dev/ -l
total 0
crw-rw-rw-.  1 root root    243,  0 May 16 19:16 altera_dma
↧

flop-flop simulation in ModelSim

May 16, 2018, 10:55 pm
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i try to simulate [1:0]flip-flop in ModelSim and i see one normal signal(out_inf[0]) and one blue signal(out_inf[1]). What is it?
Attached Images
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OpenCL compiler crashed when compile some piece of simple code

May 17, 2018, 3:34 am
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0
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Hi there, I got some trouble when I was trying to compile some complex OpenCL program with Intel FPGA OpenCL Offline Compiler.

then compiler crashed, so I try to remove some code to examine this problem, finally I got a piece of simple test code which could result in crash of compiler:

Code:
void testB(ulong8 p, ulong8 h, ulong h8, const ulong* restrict t)
{
    ulong4 p1;
    ulong8 p2;
   
    p1 = shuffle((ulong4)h8, (ulong4)44);
    p2 = shuffle2(p, h, (ulong8)55);
}


__kernel void testA(__global uint8* p)
{
    ulong ta[5]={0};
    testB(1,2,3,ta);
}
It looks like the OpenCL builtin functions like shuffle and shuffle2 caused the crash

The command line that I used to compile is:
Code:
aoc -v -g --report skein.cl
The compiler version is:
Code:
Intel(R) FPGA SDK for OpenCL(TM), 64-Bit Offline Compiler
Version 17.0.0 Build 290
Copyright (C) 2017 Intel Corporation
The compile log will be posted with attachment.

Is there anyone got same problem as me ?
thanks for your time.
Attached Files
↧

Accessing UART JTAG programmatically

May 17, 2018, 3:54 am
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Hello,
I have a Cyclone V FPGA and it has a USB JTAG. I want to access the JTAG programmatically using python script. Is there any DLL (and the documentation) exposed by Altera to access JTAG?
I am able to perform source level debug on this Cyclone V FPGA, which means the JTAG is fully functional.
↧

Custom type simulation

May 17, 2018, 4:30 am
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0
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Hi,
in my VHDL design I have custom type:

type T_STATE is (STOPPED, STARTED, RUNNING);
signal state: T_STATE;

In Simulation Waveform editor I want to see value of state signal so I go to Insert Node or Bus and I add state signal so it appears in the left column of Simulation Waveform Editor. I run simulation, however the value of state signal is always u (undefined probably). I'm sure state has always some value (STOPPED or STARTED or RUNNING). Can you please help how to display value of custom type in Simulation waveform editor?
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