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little problem in understanding MODULAR sgDMA ?

May 17, 2018, 8:06 am
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hello all,

I have created a SoC in platform designer which have a modular SG-DMA. I have a confusion on what to pass the arguments while using HAL API function calls.

ex: alt_msgdma_standard_descriptor_async_transfer( argument 1 , argument 2);

argument 1 : it is simply a pointer to msgdma instance (i have clarity on this)
argument 2 : <alt_msgdma_standard_descriptor *desc> which says *desc : a pointer to a standard descriptor structure.

In the address editor of qsys tool , descriptor port of msgdma has 0x0208_1040 address.

what should i give in this argument 2. ???

The same confusion while using another API : alt_msgdma_construct_standard_mm_to_mm_descriptor (arg1,arg2,arg3,arg4,arg5,arg6);
arg1 : device instance
arg2 : a pointer to a standard descriptor structure (????)
arg3 : read_address
arg4 : write_address
arg5 : length
arg6: control

coming to hardware part, It has nios, ocm,msgdma, myown 4kb memory (burst capable) acts as source, another instance as destination.

I am attaching c file and as well as qsys IP integration.

my questions are
1. am i missing any other function call
2. how to use the arg2 as i asked above.
3. any fundamental mistake is there in my SoC ,please check zip file.

please somebody help me to sort out this issue.


Hope this will resolve this time at-least.
Thanks
Anil
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Access SDRAM in Altera DE2 Board

May 17, 2018, 8:45 am
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Hello,

I am trying to setup a NIOS project and I would like to use the SDRAM on the board.
Unfortunately, I seem to be unable to access the chip.
When trying to store the software on the chip, I get the classical "Verify failed" error.
I tried the memtest template and apparently, it fails right at the start with "Data bus test failed at bit 0x1".
As far as I understand, this means that my SDRAM configuration is wrong.
Unfortunately, I don't see where. I have a PLL ensuring that the SDRAM clock leads all other clocks and the pins are well configured.

I attached my project to this post.

Thanks in advance,
Fofeu
Attached Files
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invalid data received when communicating over ULPI bus

May 17, 2018, 9:30 am
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I have implementing simple FPGA-design that tries to read vid/pid register from ULPI PHY presented on DECA board over ULPI bus. This project is available here https://gitlab.com/vvavrychuk/deca-ulpi.

But unfortunately my project is not working correctly. I am able to read only VID_LOW (address 0). See attached ulpi.png file. When I try to read value of other VID_HIGH, PID_HIGH and PID_LOW, I am still receiving value of VID_LOW. Do you have any idea what can be cause of such behaviour?

Another anomaly that I noticed is that usb_ulpi_nxt is set on the same tick as I put usb_ulpi_data. As far as I understand from ulpi_doc_timing.png usb_ulpi_nxt bit should be set on the second tick after start of usb_ulpi_data transmission from us. This is very strange for me that usb_ulpi_nxt is set on the same tick as data started to be streamed from usb_ulpi_data.
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EPCQ replacing EPCS128

May 17, 2018, 10:16 am
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I use a Arria V with an EPCS128. When I replaced it with an (Altera) EPCQ128, it programs/verifies fine (.jic using 13.1 programmer) but the Arria won't start when I power-cycle. I was hoping to find a drop-in replacement that would not require a change to the code. Would another-version stand-alone programmer help? Thas
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Autogenerated altshift taps

May 17, 2018, 11:33 am
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Dear Developers,
I am creating a code where I used memory , however there is a part of memory that I didn't actually use , it is "auto generated" called altshift taps as shown in image, Kindly I need a justification for adding it by Quartus.
Many thanks.
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SPI slave clock crossing domain?

May 17, 2018, 9:25 pm
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I have a question about synchronization between clock domains in SPI slave.
I need to design a SPI slave module, which has SS (slave select), SCK (SPI clock), SDI (data in from master), SDO (Data out from SPI slave). Also, in SPI slave module, it has a system clock name CLK.
In SPI slave module, it has two clock domains: SCK and CLK. Those clocks are asynchronous, and frequency of CLK is much faster than frequency of SCK (frequency of CLK is 200Mhz, frequency of SCK is maximum 20MHz).

I am intending to use 2 D-FlipFlops to synchronize SS, SCK, SDI from SPI clock domain to system clock domain, and all processing of SPI logic is handled in system clock domain (edge detection, FSM,... will be done at system clock domain).

Could anyone answer me the following question?
1. Is it OK if I use 2 D-FFs for synchronizing SS, SCK, SDI separately (2 D-FFs for SS, 2 D-FFs for SCK, 2 D-FFs for SDI)?
2. After synchronization, at system clock domain, is there any possibility that SS, SCK and SDI signal do not have the same format as original SPI transaction?
For example
At SPI clock domain: Original SPI transaction: SS (High) -> SS (Low) -> SCK and SDI are input (L-> H -> L -> ...)
At system clock domain: after synchronization: SS (High) -> SCK and SDI are input (L-> H -> L -> ...) -> SS (Low)

I ask question 2 because I use 2 D-FFs for synchronizing SS, SCK, SDI separately. During synchronization, SS meets a meta-stability problem, so SS comes lately compare to SCK and SDI.
It means that at system clock domain, the SPI transaction is not same as SPI clock domain.

I am a newbie of SPI design. So my question may be amateur. But I think it is a basic question for SPI slave design.
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How can I activate these IP in QSys?

May 17, 2018, 9:52 pm
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How can I activate these IP in blue circle in QSys?
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Pl-usb-blaster-rcn

May 18, 2018, 1:29 am
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Hi need help regarding this part PL-USB-BLASTER-RCN.
Our customer bought this part in Decembr2017 and It was working fine until recently

Now they are getting below error

ID 209025 Cannot recognize silicon ID for device 1.
ID 209012 Operation failed

please help to advice, what does this mean?
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Progress FAILED !!! on the programmer.

May 18, 2018, 1:29 am
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Hello Guys;

I have a problem, I can use Quartus Prime Lite Edition 15.1 so MY Project is created file that are .sof and .pof by Quartus Prime Lite Edition.

I want to program my evaluation kit , I open programmer and set up hardware setup. I can look USB-Blaster-II and my evaluation kit property so

I choose .sof file and click Start button. Progress is failed.

Why did programmer occur error?
WHAT should I do for programming file succesfully ??

Thank u .
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sector erase err with asmi_parallel IP core

May 18, 2018, 1:45 am
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HI
I can write and read with asmi_parallel IP core, but after I set sector_erase command , the data in the epcs128 are not 0xFF
my signal wave is as attached picture

what's the problem maybe? I have read the status register, it is 0x00
Can anyone help me?!Thanks a lot
Attached Images
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Hello world program hangs :(

May 18, 2018, 3:48 am
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I have generated the binary file of the hello world program. I have used the host program to launch it. However, it never completes. It gets stuck at the line
status = clFinish(queue);

Here is my output of the program.

manoj@EV-PHD-ROS-PC:~/Documents/exm_opencl_hello_world_x64_linux/hello_world/bin$ ./host
Querying platform for info:
==========================
CL_PLATFORM_NAME = Intel(R) FPGA SDK for OpenCL(TM)
CL_PLATFORM_VENDOR = Intel(R) Corporation
CL_PLATFORM_VERSION = OpenCL 1.0 Intel(R) FPGA SDK for OpenCL(TM), Version 17.1.2

Querying device for info:
========================
CL_DEVICE_NAME = a10gx : Arria 10 Reference Platform (acla10_ref0)
CL_DEVICE_VENDOR = Intel(R) Corporation
CL_DEVICE_VENDOR_ID = 4466
CL_DEVICE_VERSION = OpenCL 1.0 Intel(R) FPGA SDK for OpenCL(TM), Version 17.1.2
CL_DRIVER_VERSION = 17.1
CL_DEVICE_ADDRESS_BITS = 64
CL_DEVICE_AVAILABLE = true
CL_DEVICE_ENDIAN_LITTLE = true
CL_DEVICE_GLOBAL_MEM_CACHE_SIZE = 32768
CL_DEVICE_GLOBAL_MEM_CACHELINE_SIZE = 0
CL_DEVICE_GLOBAL_MEM_SIZE = 2147483648
CL_DEVICE_IMAGE_SUPPORT = true
CL_DEVICE_LOCAL_MEM_SIZE = 16384
CL_DEVICE_MAX_CLOCK_FREQUENCY = 1000
CL_DEVICE_MAX_COMPUTE_UNITS = 1
CL_DEVICE_MAX_CONSTANT_ARGS = 8
CL_DEVICE_MAX_CONSTANT_BUFFER_SIZE = 536870912
CL_DEVICE_MAX_WORK_ITEM_DIMENSIONS = 3
CL_DEVICE_MEM_BASE_ADDR_ALIGN = 8192
CL_DEVICE_MIN_DATA_TYPE_ALIGN_SIZE = 1024
CL_DEVICE_PREFERRED_VECTOR_WIDTH_CHAR = 4
CL_DEVICE_PREFERRED_VECTOR_WIDTH_SHORT = 2
CL_DEVICE_PREFERRED_VECTOR_WIDTH_INT = 1
CL_DEVICE_PREFERRED_VECTOR_WIDTH_LONG = 1
CL_DEVICE_PREFERRED_VECTOR_WIDTH_FLOAT = 1
CL_DEVICE_PREFERRED_VECTOR_WIDTH_DOUBLE = 0
Command queue out of order? = false
Command queue profiling enabled? = true
Using AOCX: hello_world.aocx
Reprogramming device [0] with handle 1
MMD INFO : Autodetect Cable not found!!
MMD INFO : setting Cable to default value 1
MMD INFO : setting Device Index to default value 1
MMD INFO : executing "quartus_pgm -c 1 -m jtag -o "P;reprogram_temp.sof@1""
Info: ************************************************** *****************
Info: Running Quartus Prime Programmer
Info: Version 17.1.2 Build 304 01/31/2018 SJ Pro Edition
Info: Copyright (C) 2018 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details.
Info: Processing started: Fri May 18 11:38:58 2018
Info: Command: quartus_pgm -c 1 -m jtag -o P;reprogram_temp.sof@1
Info (213045): Using programming cable "USB-BlasterII [3-3]"
Info (213011): Using programming file reprogram_temp.sof with checksum 0x308535CE for device 10AX115S2F45@1
Info (209060): Started Programmer operation at Fri May 18 11:39:05 2018
Info (209016): Configuring device index 1
Info (209017): Device 1 contains JTAG ID code 0x02E060DD
Info (209007): Configuration succeeded -- 1 device(s) configured
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Fri May 18 11:39:20 2018
Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 1685 megabytes
Info: Processing ended: Fri May 18 11:39:20 2018
Info: Elapsed time: 00:00:22
Info: Total CPU time (on all processors): 00:00:11

Kernel initialization is complete.
Launching the kernel...
and never completes. I see that the kernel is launched. But it waits for the events to get completed.

And whenever I use aocl program command I get
MMD INFO : Autodetect Cable not found!!
MMD INFO : setting Cable to default value 1
MMD INFO : setting Device Index to default value 1
MMD INFO : executing "quartus_pgm -c 1 -m jtag -o "P;reprogram_temp.sof@1""

For some reason PCIe is not being used to program. When I cancel and quit the session, I have to kill the jtagd, and use quartus_pgm -a in order to reprogram. Otherwise I get
Error (213013): Programming hardware cable not detected



Why? Am I doing something wrong. Is this because of PCIe connection? I have checked lspci | grep Altera and everything seems to be alright!

lspci | grep Altera
03:00.0 Processing accelerators: Altera Corporation Device 2494 (rev 01)



Regards,
Manoj.
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Read FIFO outside Qsys design via Nios II

May 18, 2018, 3:55 am
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A block outside the Qsys system generates data which can be read from a FIFO. Thus, the exposed interface is q, empty, rdreq. I want to connect Qsys to this design and read the data generated by this block and written into its FIFO.

Since the FIFO is external the Qsys system, I could connect to it via PIO. However, I am sure that a superior method exists to achieve this end. How should this be done?
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How to sum sine waves up by using IP blocks

May 18, 2018, 4:51 am
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Hi, My task was to create two different freq. sine waves and sum them up. I defined them as signals but how to sum them by using IP clocks? Can some please help me? You can take a look to my code in attached vhd file. Thx in advance
Attached Files
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OpenCL 18.0 version

May 18, 2018, 10:33 am
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Hi everyone,
I have seen that in the new version 18.0 the compiler can generate an additional file with extension ".aocr". Can anyone explain me this new aspect? Thanks

Marco Montini
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Error Of configuration NIOS II fpga

May 18, 2018, 10:53 am
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Hello,

I build a simple code like a counter of leds or seven segment and it build succesful but when I want to impliment the code in My FPGA nothing happen in my FPGA .
And this message appear during my running.

there are some attachement
I dont know actually what is the problem ..pleaase help me .
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Using registers to debug in SignalTap

May 18, 2018, 10:56 am
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I've been using this technique for several months, and I'm curious if anyone else does the same or if there is a better way.

When I want to track a signal in SignalTap, I do the following:
  1. Add a RegOut block to my model and give it a name like "DebugFIFODataOut".
  2. Generate DSP Builder, Qsys, and run Synthesis
  3. In SignalTap, search for *debugfifodataout* with filter set to Design Entry (all names).
  4. Drill down to the busSlaveFabric_*
  5. Insert the in_AMMregisterPortData* and in_AMMregisterPortWriteEn*
  6. Add meaningful Aliases to the signals


Note that you can use the write signal on the register as well as you are not actually concerned with register itself.
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Arria 10 SoC DevKit - IP for building GSRD hardware design

May 18, 2018, 10:56 am
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I'm trying to follow the getting started steps for building the GSRD hardware design on an Arria 10 SoC Devkit.
( https://rocketboards.org/foswiki/Doc...dwareDesign171 )

I'm getting errors that I don't have valid licenses for the DisplayPort and one other Video-related IP. I do have the "Quartus Pro Edition for Development Kits" license that came with the DevKit. In order to even follow the "Getting Started" steps, specifically compiling the GSRD hardware design, do I need to purchase an additional license?
(Note that I mean for compiling the hardware design while *not* on the Intel corporate network. I'm trying to understand the license requirements for successfully following the "Getting Started" steps for a general user/purchaser.) I noticed that even the "Begin 30-day grace period" is grayed-out on the license setup page in Quartus.

If I don't need an additional license, any thoughts as to why I'm getting this error for the GSRD design?
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RS232 communication with DE4 NIOSII

May 18, 2018, 2:36 pm
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Hi,
I'm trying to access(read/write) to CPU on DE4 board via RS232. The Quartus project and Qsys is fine but I need write C code in a way that the some strings from PC be written to on cheap memory with interrupt. Does anyone know how should I write this part of my code?

Thanks
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No Altera Monitor Program for Quartus 17.0?

May 19, 2018, 3:04 am
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There is the 'Using Triple Speed Ethernet on De2-115 Boards' tutorial for Quartus 17.0, tells us to use the Altera Monitor Program at the end, yet Altera Monitor Program has only up to version 16.1.

I tried to install the Altera Monitor Program 16.1 on Quartus 17.0 directory and tested, and it kept popping JTAG errors.

So... Altera Monitor Program does not support Quartus 17.0 at all?
Has anyone tried to use it with Quartus 17.0?
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DDR DQS BANKS 5/6 MAX10 Conflict

May 19, 2018, 3:07 pm
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In the MAX10M16 the two banks that support DDR memory are bank 5/6.
The DQS lines for banks 6 is on pins H11/H12.
The DQS lines for banks 5 is on pins L15/K15.

If i assign the DQS/DQ on bank 6 (pins H11/H12)
I get an error that says:
Error (171082): Can't place node "mem_dqs[0]" in location or region "PIN L15" -- location is not compatible with current location of PIN H11 for the node -- location added due to User Location Constraints and IO standards pin placement

If i assign the DQS/DQ on bank 5 (pins L15/K15)
I get an error that says:
Error (171082): Can't place node "mem_dqs[0]" in location or region "PIN H11" -- location is not compatible with current location of PIN L15 for the node -- location added due to User Location Constraints and IO standards pin placement

... so i am stuck. What bank should i put my DQS/DQ pins on?

Is there something i need to do to the DQS pins that are not used?
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