moduleSLAVE_FIFO_STREAM_IN(
input CLOCK_50, //input clp 50 Mhz
inout [31:0] FX3_DQ, //data bus
output [1:0] FX3_faddr, //output fifo address
output FX3_slrd, //output read select
output FX3_slwr, //output write select
input FX3_flaga, //full flag
input FX3_flagb, //partial full flag
input FX3_flagc, //empty flag
input FX3_flagd, //empty partial flag
output FX3_sloe, //output output enable select
output FX3_CLK, //output clk 100 Mhz and 180 phase shift
output FX3_slcs, //output chip select
output FX3_pktend, //output pkt end
output [1:0] FX3_PMODE,
output FX3_RESET,
output FX3_PMODE_2 //used fordebugging
);
set_time_format-unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -nameCLOCK_50M -period 20.000 [get_ports {CLOCK_50}]
create_generated_clock\
-nameCLOCK_100M \
-multiply_by 2\
-source[get_pins {pll_inst|altpll_component|auto_generated|pll1|inclk[0]}] \
[get_pins{pll_inst|altpll_component|auto_generated|pll1|clk[0]}]
#**************************************************************
# Create GeneratedClock
#**************************************************************
# Put a generatedclock on output clock port to be referenced by set_output_delay constraints. Note the -invert option, which says the clock is being inverted on theway out. This is important
# since Quartusdoesn't recognize the DDR output with VCC/GND switched as inverting the clock
create_generated_clock-source [get_pins {pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -nameCLOCK_FX3 [get_ports {FX3_CLK}] -invert
set_false_path -to[get_ports {FX3_CLK}]
#Constrain the PLLautomatically
derive_pll_clocks-create_base_clocks
#**************************************************************
# Set ClockUncertainty
#**************************************************************
derive_clock_uncertainty
################################################################################
#Parameters
################################################################################
# Specify themaximum external clock delay to the FPGA
set FX3_CLKs_max 0
# Specify theminimum external clock delay to the FPGA
set FX3_CLKs_min 0
# Specify themaximum external clock delay to the external device
set FX3_CLKd_max 0
# Specify theminimum external clock delay to the external device
set FX3_CLKd_min 0
# Specify themaximum setup time of the external device
set FX3_tSU 2
# Specify theminimum setup time of the external device
set FX3_tH 0.5
# Specify themaximum board delay
set FX3_BD_max 0
# Specify theminimum board delay
set FX3_BD_min 0
# Specify themaximum clock-to-out of the external device
set FX3_tCO_max 9
# Specify theminimum clock-to-out of the external device
set FX3_tCO_min 2
################################################################################
#Output constraints
################################################################################
set_output_delay-clock CLOCK_FX3 -max [expr $FX3_CLKs_max + $FX3_BD_max + $FX3_tSU -$FX3_CLKd_min] [get_ports {FX3_slcs FX3_slwr FX3_sloe FX3_slrd FX3_pktendFX3_faddr* FX3_DQ*}]
set_output_delay-clock CLOCK_FX3 -min [expr $FX3_CLKs_min + $FX3_BD_min - $FX3_tH -$FX3_CLKd_max] [get_ports {FX3_slcs FX3_slwr FX3_sloe FX3_slrd FX3_pktendFX3_faddr* FX3_DQ*}] -add_delay
################################################################################
#Input constraints
################################################################################
set_input_delay-clock CLOCK_FX3 -max [expr $FX3_CLKs_max + $FX3_tCO_max + $FX3_BD_max -$FX3_CLKd_min] [get_ports {FX3_DQ* FX3_flaga FX3_flagb}]
set_input_delay-clock CLOCK_FX3 -min [expr $FX3_CLKs_min + $FX3_tCO_min + $FX3_BD_min -$FX3_CLKd_max] [get_ports {FX3_DQ* FX3_flaga FX3_flagb}] module pb_sensor_emulator(
input wire clk,
input wire rst_n,
input wire button_in,
//output wire sensor_out
output reg sensor_out
);
reg sensor_reg;
/* debounce & detect edge of button */
wire button_edge;
reg button_in_d1;
reg button_db = 1'b0;
// debounce
debouncer deb(
.clk(clk),
.PB(button_in),
.PB_state(button_db)
);
// detect edge
always @(posedge clk)
begin
button_in_d1<=button_db;
end
assign button_edge = button_db & ~button_in_d1;
/********************************/
/* define states for sensor emulator FSM */
enum logic {OFF = 1'b0, ON = 1'b1} state, nextstate;
/* state transitions */
always_ff @(posedge clk or negedge rst_n)
begin
if (!rst_n)
state <= OFF;
else
state <= nextstate;
end
/* state outputs */
always_comb
begin
/* set defaults */
sensor_out = 1'b0;
/* begin output combinational logic */
case(state)
OFF:
begin
end
ON:
begin
sensor_out = 1'b1;
end
endcase
end
/* next state logic */
always_comb
begin
/* default next-state */
nextstate = OFF;
/* begin next-state combinational logic */
case(state)
OFF:
begin
if(button_edge)
nextstate = ON;
else
nextstate = OFF;
end
ON:
begin
if(button_edge)
nextstate = OFF;
else
nextstate = ON;
end
endcase
end
endmodule