Quantcast
Channel: Altera Forums
Viewing all 19390 articles
Browse latest View live
↧

USB Blaster stopped working with Windows 10 update?

May 22, 2018, 5:26 am
$
0
0
So it may be just a coincidence but last week everything was working good. On Friday my system updated with the latest Windows 10 1803 update and I noticed in Quartus ver 17.1 and the standalone programmer that i could no longer see the USB blaster. I tired another USB blaster and the same issue. The Device Manager shows the USB Blaster under the USB devices and says it's working normal. Thinking maybe i had a corrupted driver I uninstalled the driver and tried reinstalling the driver using the one that gets installed with the software and I got an error saying Windows has encountered a problem installing the driver, Access is denied. I am a full admin on this system so i don't feel "rights" is an issue. So i tried rebooting the computer and disables driver signature enforcement and that didn't help. I tired to uninstall the 1803 WIndows update but Windows came back saying that it can't be uninstalled. I downloaded the latest ver 18 standalone programmer and tried that driver and no change, same error.
So wondering about admin rights i tried two other computers in my lab that had the 1803 update as well and I got the same problem tried to do a clean install of the USB blaster. I found one computer that was still at the Windows 10 1709 update and tried installing the driver. Here I got the issue where it tells me the hash for the file is not present, so i rebooted the computer and disables driver signature enforcement and was able to install the driver and reboot as normal with everything working. I'm on a domain so the computer has to be up to date so even rebuilding the computer and not do the 1803 update isn't an option. Anyone else have this issue?
↧
Search

Quartus 17.1 Lite Launch Crash on XUbuntu 14.04

May 22, 2018, 5:34 am
$
0
0
Hello everyone,
I installed Quartus recently on a Linux machine in my University.
The installation completed without problem and I can launch the program without any problems if I am logged in as administrator.
If I launch Quartus as guest User it crashes instantly and the Report stats:

Problem Details
Error:


*** Fatal Error: Segment Violation at (nil)
Module: quartus
Stack Trace:
0xe0a80: Ox3476f84b43216cbb + 0x50 (sys_cpt)


0xb28a8: Ox3476f8367c6535b1 + 0xc8 (sys_cpt)


0xa3b47: lc_getid_type + 0x57 (sys_cpt)
0x560d3: cpt_flexlm_get_local_hostid_by_type + 0x5e (sys_cpt)
0x56224: cpt_flexlm_get_local_hostid + 0x13 (sys_cpt)
0x395e1: CPT_FLEXLM_MGR::get_local_hostid(CPT_HOSTID_TYPE, std::vector<std::string, std::allocator<std::string> >*) + 0x41 (sys_cpt)
0x3d8be: CPT_MANAGER::get_local_hostid(CPT_HOSTID_TYPE, std::vector<std::string, std::allocator<std::string> >*) + 0xa6 (sys_cpt)
0x18507: cpt_guiq_append_url_args(std::string&) + 0x1eb (sys_cpt_guiq)
0x18dd5: cpt_guiq_ping_web_edition_tracker() + 0x21 (sys_cpt_guiq)
0xba1b: cpt_guiq_dyn_init + 0x1bb (sys_cpt_guiq)
0x6829e: QUI_APP::init_instance(int, char const**, QUI_CMDLINE*) + 0x3ec (sys_qui)
0x1202d: QGQ_APP::init_instance(int, char const**, QUI_CMDLINE*) + 0xdf (sys_qgq)
0x1e9f: qgq_main(int, char const**) + 0x5f (quartus)
0x40720: msg_main_thread(void*) + 0x10 (ccl_msg)
0x602c: thr_final_wrapper + 0xc (ccl_thr)
0x407df: msg_thread_wrapper(void* (*)(void*), void*) + 0x62 (ccl_msg)
0xa559: mem_thread_wrapper(void* (*)(void*), void*) + 0x99 (ccl_mem)
0x8f92: err_thread_wrapper(void* (*)(void*), void*) + 0x27 (ccl_err)
0x63f2: thr_thread_wrapper + 0x15 (ccl_thr)
0x427e2: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0xa3 (ccl_msg)
0x1f7a: main + 0x26 (quartus)
0x21ec5: __libc_start_main + 0xf5 (c.so.6)




End-trace

I'm thinking that it might be permission related, although I checked and the permissions seem to be the same with Quartus as with programs that run as guest.
But I am not 100% sure because I am not too confident with linux. Quartus 13.1 Lite is also installed, and it works fine.
Maybe one of you guys know a solution.
↧
↧

SDI II Interface Altera

May 22, 2018, 6:24 am
$
0
0
Dear All, Hope you all are well. I would like to have an idea to implement TRS(Timing reference signal) the way SDI II interface has implemented. How to bind those default TRS data with every input using VHDL ? Which function does it support?
Thanks in advance.


Bets regards,
Nizam
↧

altera.com/bin/myAlteraAuth shut down

May 22, 2018, 8:46 am
$
0
0
Soon as a week as I can not enter the site altera.com to download the Quartus software. I ask for advice and assistance, because the webmaster does not respond.
↧

Adding nets to signaltap via HDL

May 22, 2018, 12:26 pm
$
0
0
Hello,

Is it possible to add nets for signaltap debugging using VHDL attributes ?
↧
↧

Cannot get JTAG Device to show up in Quartus

May 22, 2018, 2:59 pm
$
0
0
I am using the S10 SoC Development Kit, with Quartus 18.0.
I cannot get the configuration hardware to show up in programmer.
I've followed the steps listed in this excellent tutorial: http://www.fpga-dev.com/altera-usb-blaster-with-ubuntu/
Any tips will be appreciated.

quartus version 18.0
>> /tools/intelFPGA_pro/18.0/quartus/bin/quartus

>> lsusb
Bus 001 Device 011: ID 0403:6001 Future Technology Devices International, Ltd FT232 USB-Serial (UART) IC

>> dmesg
[ 1153.023826] usb 1-13: FTDI USB Serial Device converter now attached to ttyUSB0

>> Ubuntu Version
Linux version 4.13.0-41-generic (buildd@lgw01-amd64-028) (gcc version 5.4.0 20160609 (Ubuntu 5.4.0-6ubuntu1~16.04.9)) #46~16.04.1-Ubuntu SMP Thu May 3 10:06:43 UTC 2018

>> strace jtagd --foreground --debug
Code:
execve("/tools/intelFPGA_pro/18.0/quartus/bin/jtagd", ["jtagd", "--foreground", "--debug"], [/* 38 vars */]) = 0
brk(NULL)                              = 0x9ef000
access("/etc/ld.so.nohwcap", F_OK)      = -1 ENOENT (No such file or directory)
access("/etc/ld.so.preload", R_OK)      = -1 ENOENT (No such file or directory)
open("/etc/ld.so.cache", O_RDONLY|O_CLOEXEC) = 3
fstat(3, {st_mode=S_IFREG|0644, st_size=89170, ...}) = 0
mmap(NULL, 89170, PROT_READ, MAP_PRIVATE, 3, 0) = 0x7fe5b6911000
close(3)                                = 0
access("/etc/ld.so.nohwcap", F_OK)      = -1 ENOENT (No such file or directory)
open("/lib/x86_64-linux-gnu/libtinfo.so.5", O_RDONLY|O_CLOEXEC) = 3
read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0p\310\0\0\0\0\0\0"..., 832) = 832
fstat(3, {st_mode=S_IFREG|0644, st_size=167240, ...}) = 0
mmap(NULL, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7fe5b6910000
mmap(NULL, 2264256, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7fe5b64d9000
mprotect(0x7fe5b64fe000, 2093056, PROT_NONE) = 0
mmap(0x7fe5b66fd000, 20480, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x24000) = 0x7fe5b66fd000
close(3)                                = 0
access("/etc/ld.so.nohwcap", F_OK)      = -1 ENOENT (No such file or directory)
open("/lib/x86_64-linux-gnu/libdl.so.2", O_RDONLY|O_CLOEXEC) = 3
read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\240\r\0\0\0\0\0\0"..., 832) = 832
fstat(3, {st_mode=S_IFREG|0644, st_size=14608, ...}) = 0
mmap(NULL, 2109680, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7fe5b62d5000
mprotect(0x7fe5b62d8000, 2093056, PROT_NONE) = 0
mmap(0x7fe5b64d7000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7fe5b64d7000
close(3)                                = 0
access("/etc/ld.so.nohwcap", F_OK)      = -1 ENOENT (No such file or directory)
open("/lib/x86_64-linux-gnu/libc.so.6", O_RDONLY|O_CLOEXEC) = 3
read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0P\t\2\0\0\0\0\0"..., 832) = 832
fstat(3, {st_mode=S_IFREG|0755, st_size=1868984, ...}) = 0
mmap(NULL, 3971488, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7fe5b5f0b000
mprotect(0x7fe5b60cb000, 2097152, PROT_NONE) = 0
mmap(0x7fe5b62cb000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1c0000) = 0x7fe5b62cb000
mmap(0x7fe5b62d1000, 14752, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7fe5b62d1000
close(3)                                = 0
mmap(NULL, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7fe5b690f000
mmap(NULL, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7fe5b690e000
mmap(NULL, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7fe5b690d000
arch_prctl(ARCH_SET_FS, 0x7fe5b690e700) = 0
mprotect(0x7fe5b62cb000, 16384, PROT_READ) = 0
mprotect(0x7fe5b64d7000, 4096, PROT_READ) = 0
mprotect(0x7fe5b66fd000, 16384, PROT_READ) = 0
mprotect(0x6f3000, 4096, PROT_READ)    = 0
mprotect(0x7fe5b6927000, 4096, PROT_READ) = 0
munmap(0x7fe5b6911000, 89170)          = 0
open("/dev/tty", O_RDWR|O_NONBLOCK)    = 3
close(3)                                = 0
brk(NULL)                              = 0x9ef000
brk(0x9f0000)                          = 0x9f0000
open("/usr/lib/locale/locale-archive", O_RDONLY|O_CLOEXEC) = 3
fstat(3, {st_mode=S_IFREG|0644, st_size=2981280, ...}) = 0
mmap(NULL, 2981280, PROT_READ, MAP_PRIVATE, 3, 0) = 0x7fe5b5c33000
close(3)                                = 0
brk(0x9f1000)                          = 0x9f1000
brk(0x9f2000)                          = 0x9f2000
getuid()                                = 1001
getgid()                                = 1001
geteuid()                              = 1001
getegid()                              = 1001
rt_sigprocmask(SIG_BLOCK, NULL, [], 8)  = 0
brk(0x9f3000)                          = 0x9f3000
sysinfo({uptime=1780, loads=[4384, 1024, 288], totalram=99814060032, freeram=98714148864, sharedram=10485760, bufferram=47362048, totalswap=101539901440, freeswap=101539901440, procs=483, totalhigh=0, freehigh=0, mem_unit=1}) = 0
brk(0x9f4000)                          = 0x9f4000
rt_sigaction(SIGCHLD, {SIG_DFL, [], SA_RESTORER|SA_RESTART, 0x7fe5b5f404b0}, {SIG_DFL, [], 0}, 8) = 0
rt_sigaction(SIGCHLD, {SIG_DFL, [], SA_RESTORER|SA_RESTART, 0x7fe5b5f404b0}, {SIG_DFL, [], SA_RESTORER|SA_RESTART, 0x7fe5b5f404b0}, 8) = 0
rt_sigaction(SIGINT, {SIG_DFL, [], SA_RESTORER, 0x7fe5b5f404b0}, {SIG_DFL, [], 0}, 8) = 0
rt_sigaction(SIGINT, {SIG_DFL, [], SA_RESTORER, 0x7fe5b5f404b0}, {SIG_DFL, [], SA_RESTORER, 0x7fe5b5f404b0}, 8) = 0
rt_sigaction(SIGQUIT, {SIG_DFL, [], SA_RESTORER, 0x7fe5b5f404b0}, {SIG_DFL, [], 0}, 8) = 0
rt_sigaction(SIGQUIT, {SIG_DFL, [], SA_RESTORER, 0x7fe5b5f404b0}, {SIG_DFL, [], SA_RESTORER, 0x7fe5b5f404b0}, 8) = 0
rt_sigprocmask(SIG_BLOCK, NULL, [], 8)  = 0
rt_sigaction(SIGQUIT, {SIG_IGN, [], SA_RESTORER, 0x7fe5b5f404b0}, {SIG_DFL, [], SA_RESTORER, 0x7fe5b5f404b0}, 8) = 0
uname({sysname="Linux", nodename="snic1", ...}) = 0
brk(0x9f5000)                          = 0x9f5000
brk(0x9f6000)                          = 0x9f6000
brk(0x9f7000)                          = 0x9f7000
brk(0x9f8000)                          = 0x9f8000
stat("/home/******", {st_mode=S_IFDIR|0755, st_size=4096, ...}) = 0
stat(".", {st_mode=S_IFDIR|0755, st_size=4096, ...}) = 0
getpid()                                = 2897
open("/usr/lib/x86_64-linux-gnu/gconv/gconv-modules.cache", O_RDONLY) = 3
fstat(3, {st_mode=S_IFREG|0644, st_size=26258, ...}) = 0
mmap(NULL, 26258, PROT_READ, MAP_SHARED, 3, 0) = 0x7fe5b6920000
close(3)                                = 0
getppid()                              = 2895
brk(0x9f9000)                          = 0x9f9000
brk(0x9fa000)                          = 0x9fa000
↧

Host to Host DMA

May 22, 2018, 3:03 pm
$
0
0
Hello,

Can somebody point me to a reference example that does a Host to Host DMA, if it exists?

I've come across the Avalon Memory Mapped DMA that does host to FPGA, and FPGA to host DMA.
I've also found reference examples with MSGDMA being controlled by NIOS.

I have not found anything that does a round-trip DMA, either Avalon MM or MSGDMA.

Any pointers will be appreciated.

Thanks,
~S.
↧

my first fpga hps

May 23, 2018, 12:00 am
$
0
0
Hello,

Im just trying to run my_first_hps_fpga but when I try to make in the shell there is an error
I dont get where is the problem
pleaase help me

there is an attachement.
Attached Images
↧
Search

More Work items - More Resource usage?

May 23, 2018, 1:16 am
$
0
0
I have tried increasing work items per work group with number of CU = 1 using the following attribute

__attribute__((reqd_work_group_size(BLOCKDIM,BLOCK DIM,1))) in the matrix multiplication example.

In first case : I have set the BLOCKDIM = 16

In the second case : I have set BLOCKDIM = 32

I get almost same resource usage and latency. The number of DSP units are also same.

I only observe propotional increase in resource usage when I increase compute units, SIMD or unrolling loops. How does work item get mapped in FPGA fabric.
↧
↧

any plans for Cyclone 10 SoC?

May 23, 2018, 1:25 am
$
0
0
Hi,
I'm planning a new project and looking for most up-to-date devices.
Are there any plans in near future to release Cyclone 10 SoC FPGAs?
Regards
↧

Digital Music

May 23, 2018, 1:58 am
$
0
0
Hy.


I want to generate some tone using de1 bord.
For that i want to store some digital tones in SRAM, and to play them with the Audio Codec. Could you please provide me some digital words for some tones. I tried several combinations, but nothing nice came out.


Thank you.
↧

idea

May 23, 2018, 2:25 am
$
0
0
Hello

I need to turn on /of a led using de1 cyclone v then receive
which led is turnon in my terminal
How can I do this ? I dont have any idea which protocole can I use

I thought of serial communication ethernet using hps fpga or just using eclipse Nios II?
pleease help which simple solution can I do ?
THANK YOU.
↧

IS this behaviour of modular sgdma correct ??

May 23, 2018, 3:26 am
$
0
0
Hello all,

I am attaching the zip file of a .jpeg image that contains snapshot of a burst transactions between two avalon memory buffers via msgdma.

Just see the i) readdata of src buffer and ii) writedata of dst buffer.

settings in msgdma : maximum burst count : 256
From sdk i am initiating 256 transfers.

one can observe that, msgdma is first reading entire source data first and then only it started writing data into destination. But when i used simple dma , reading and writing data burst transfers happened closely.

I have a doubt on this transfer type of msgdma. If this is the case, i cant waste these many cycles.

regards,
Anil
Attached Files
↧
↧

HPS SPI remapped to FPGA cause system hangup

May 23, 2018, 8:06 am
$
0
0
Hi all!

Up untill now I've successfully used SPI master remapped to FPGA pins with CS pin via PIO. In my u-boot.scr I had such coded:
Code:
fatload mmc 0:2 $fpgadata UniDAS.rbf;
fpga load 0 $fpgadata $filesize
mw $axibridge ${axibridge_handoff};
mw $l3remap ${l3remap_handoff}
Now I'm trying to enable FPGA to HPS SDRAM bridge so I change code to this:
Code:
fatload mmc 0:2 $fpgadata UniDAS.rbf;
fpga load 0 $fpgadata $filesize
run bridge_enable_handoff;
With system console and JTAG-to-AvalonMM I verified that bridge is working fine. But! Now when I try to send data over SPI (via Linux spidev) Linux hangs and reboot. U-Boot and Preloader are both updated to match firmware.
Connections:


Maybe any one has clues what it may be?
Attached Images
↧

Automatic emails for subscriptions

May 23, 2018, 10:15 am
$
0
0
As a heads up the forum might not be sending out emails for threads you are subscribed to. So if you ask a question in the forum I recommend bookmarking the thread and periodically checking it to see if someone posted.
↧
Search

Unused qsys module causes fitter failure

May 23, 2018, 11:12 am
$
0
0
My design contains up-to 4 DDR interfaces each is defined by emif qsys module.
The project file adds a different emif qsys file to the project for each DDR interface.
In general I build with only one DDR interface instantiated, this is done with an `ifdef that removes the instantiation of the other DDR interfaces.

When I build with any of the DDR interfaces removed from the design the fitter fails with an error :
Error: The auto-constraining script was not able to detect any instance for core < p510t_bank3_altera_emif_arch_nf_170_iamurii >

The problem is that the automated build flow may build a configuration that has one or more DDR interfaces not instantiated.
I dont want to have a different project file for each configuration.

Is there a way for the fitter to not use the scripts from a qsys module that is not instantiated?
↧

Workflow tips in Simullink

May 23, 2018, 1:23 pm
$
0
0
Finally figured this out today. If you have a branching signal that you want to delete only a portion of, paste a simple block, like a sample delay, in the spot you want to snip the signal. Then delete the block. This will split the signal. If there is a better way to do this let me know.

Another workflow tip. If you want to swap out two versions of a subsystem with the same inputs and outputs, use Ctrl-x to cut the first one out. Then you can drag the other one in and all the signals will automatically reconnect. This saves time over disconnecting and re-connecting each signal manually. I commonly keep multiple variations of a subsystem commented out to test changes.

Anyone have similar tips?
↧
↧

Can Arria 10's FMC single-ended signals be more than 2.0 V?

May 23, 2018, 1:50 pm
$
0
0
Hi,

I'm wondering if I can get more than 2.0V single-ended signals out of the FMC connector on the Arria 10 SOC, which using the 10AS066N3F40E2SG.
All FMC pins on this board are connected to banks 3F and 3A and the figure 77 of the "Arria 10 General Purpose I/Os Handbook" (attached below) said these banks are LVDS I/O banks, which support 1.8V single-ended signals. So my assumption is the maximum single-ended voltage signal I can get is 1.8V. If that is the case is there any way to get more than 2.0V signal out of the FMC?

Thanks

Arria 10 General Purpose I/O Handbook: https://www.altera.com/en_US/pdfs/li...0_handbook.pdf
↧

F2H Avalon Bridge f2h_sdram0_data_waitrequest got stuck

May 23, 2018, 5:59 pm
$
0
0
Hi all,

I met a problem hope someone can help.

I am using f2h_sdram0 to access the SDRAM. After building HPS system, I got the hps.xml file in handoff folder, part of the code is:

<config name='F2SDRAM_COMMAND_PORT_USED' value='0x1' />
<config name='F2SDRAM_READ_PORT_USED' value='0x3' />
<config name='F2SDRAM_WRITE_PORT_USED' value='0x3' />
<config name='F2SDRAM_RESET_PORT_USED' value='0x133' />

So looks like I have initialized the F2SDRAM reset signals. But sometimes the f2h_sdram0_data_waitrequest signal will always be high voltage?

So which option in HPS settings can change or influence that? Or it's because of some u-boot related issues?

Thank you
↧

F2H Avalon Bridge f2h_sdram0_data_waitrequest got stuck

May 23, 2018, 6:00 pm
$
0
0
Hi all,

I met a problem hope someone can help.

I am using f2h_sdram0 to access the SDRAM. After building HPS system, I got the hps.xml file in handoff folder, part of the code is:

<config name='F2SDRAM_COMMAND_PORT_USED' value='0x1' />
<config name='F2SDRAM_READ_PORT_USED' value='0x3' />
<config name='F2SDRAM_WRITE_PORT_USED' value='0x3' />
<config name='F2SDRAM_RESET_PORT_USED' value='0x133' />

So looks like I have initialized the F2SDRAM reset signals. But sometimes the f2h_sdram0_data_waitrequest signal will always be high voltage?

So which option in HPS settings can change or influence that? Or it's because of some u-boot related issues?

Thank you
↧
Viewing all 19390 articles
Browse latest View live
Search
<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>