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ADC recommendation for DE2-115

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I am now working on a project on FPGA-based PMU which require to use AC-Power as ADC input. I've googled for a while but these parameters of ADC really confuse me a lot. Terasic's THDB AD cards perform bad when frequency lower than 1Mhz. Is there any recommendations on AD cards that can be supported by DE2-115 (e.g connected by HSMC or GPIO) and have good performance on low input frequency(around 50,60hz)?

Can someone help me ASAP, thanks a lot.

Water Washability of EPM3064ATI100-10N

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We are planning to move from No Clean to Aqueous cleaning in the manufacturing process.


Is EPM3064ATI100-10N water washable with"de-ionized" water


I see no indication of water / aqueous wash ability of EPM3064ATI100-10N on the part's home page, nor in the datasheet.

Quartus 18 MegaWizard issue

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Hi all!

I just have installed Quartus 18.0.0 to test it and got an issue with MegaWizard Plugin.

I am using Ubuntu 16.04 X86_64 machine.

What I do:
1. Create a new empty project with Quartus.
2. Select MAX 10 DE10-Lite board.
3. Add LVDS IP Core to the project with some parameters.
4. Close LVDS MegaWizard PlugIn window.
5. Attempt to open LVDS IP for edition from 'IP Components'.

What I get:
"Failed to launch MegaWizard Plug-In Manager. Soft LVDS Intel FPGA IP v18.0 could not be found in the specified library paths."

See screen shot:


I did not have similar issue with Quartus 17.* on the same machine.

Any ideas?
Attached Images

make the system cannot find the file specified

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Itry to run the project in DEmonstrations SOC-fpga-my first _hps_fpga flowing the same steps like this project :https://www.youtube.com/watch?v=2WUkEt4-Q7Q
My operationg system is windows8.1
I used shell commend nios II LIKE IN THE TUTORIAL BUT:
when I launch make
arm-linux-gnueabihf-gcc-static-g-wall -I/ip/altera/hps/altera_hps/hwlib/include -c main.c -o-main.o
process began :create Process<NULL, arm-linux-gnueabihf-gcc-static-g-wall -I/ip/altera/hps/altera_hps/hwlib/include -c main.c -o-main.o ---> failed
the error was : make <e=2> the system cannot find the file specified .
MY MAKEFILE IS :

TARGET = my_first_hps




CROSS_COMPILE = arm-linux-gnueabihf-
CFLAGS= -g -Wall -l ${SOCEDS_DEST_ROOT}/ip/altera/hps/altera_hps/hwlib/include




LDFLAGS= -g -Wall




CC=$(CROSS_COMPILE)gcc




ARCH=arm




all:$(TARGET)




$(TARGET):main.o $(CC)$(LDFLAGS) $^ -o $@




%.o: %.c $(CC)$(CFLAGS) -c $< -o $@




.PHONY:clean




clean: rm -f $(TARGET)*.a.*o*~
thank u
help me please

arm-linux-gnueabihf-

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Hello ,
Ihave a problem Im looking for help please.

Im doing my first_hps.following the tutorial pdf but I have an error.
my operating system is WINDOWS 8.1
I m using the shell command of nios II
MY board is cyclone V
my problem was :
when I launch make
arm-linux-gnueabihf-gcc-static-g-wall -I/ip/altera/hps/altera_hps/hwlib/include -c main.c -o-main.o
process began :create Process<NULL, arm-linux-gnueabihf-gcc-static-g-wall -I/ip/altera/hps/altera_hps/hwlib/include -c main.c -o-main.o ---> failed
the error was : make <e=2> the system cannot find the file specified .

My makefile was :
TARGET = my_first_hps




CROSS_COMPILE = arm-linux-gnueabihf-
CFLAGS= -g -Wall -l ${SOCEDS_DEST_ROOT}/ip/altera/hps/altera_hps/hwlib/include




LDFLAGS= -g -Wall




CC=$(CROSS_COMPILE)gcc




ARCH=arm




all:$(TARGET)




$(TARGET):main.o $(CC)$(LDFLAGS) $^ -o $@




%.o: %.c $(CC)$(CFLAGS) -c $< -o $@




.PHONY:clean




clean: rm -f $(TARGET)*.a.*o*~

pleaase help me to focus the problem and go well my project.

need set_max_delay understanding

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Hi all,

Can please some one explain that what is set_max_delay and what will happen it if is used on two clocks to meet setup slack inside FPGA?

Kind regards
Mohsin

$100 for your input!

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Hello Community Members!

We are investigating a remodel of all of Intel's communities - software, tech products, FPGA products - and we'd love your input! If you'd like to be part of a small focus group, then read on:

What we’ll be doing:
A small focus group to evaluate Intel’s new Community structure. You will be doing an exercise to move forums around into the order that makes the most sense. There's actually 2 exercises but the other is super short.

Looking for people with this background:
People that log in to the communities fairly often.

Time Commitment: 60-75 minutes
When: Within the next month. We'll find a time that works for most folks.

Email us at webmaster@intel.com if you're interested! Limited # of spots. Thanks!

S10 SoC does not show up in lspci

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The S10 SoC Development board is connected to a host PC via FMC2PCIe Cables.
When the board is powered-on, but not programmed it does not show up in lspci on the host.

This is different from my experience with Bittware and other boards, where an unprogrammed FPGA shows up as a Bittware device in lspci.
After programming, and installing an Altera driver, such as in AN690, the Bittware FPGA shows up as an Altera device.

Further, when I program the S10 SoC FPGA, it still continues to not show up in lspci.
I suspect my problem is what I have described above: i.e. an unprogrammed S10 SoC board does not show up in lspci, on being powered on.

Any insights on how to debug this will be appreciated!

Pcicard error! Communication failure! Error code : 002

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Hi Sir,

I wanted configure FPGA (cyclone I) 32 bit with conventional pci. With my verilog code it is detecting the driver, but it is not transfering the data to my pci card. when we run the application it shows the error "Pcicard error! Communication failure! Error code : 002". can anyone help me plz.
I am using quartus 2 version 10.1 software to program the serial configuration device.

Error in Quartus' Simulation Editor

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I'm doing a project using Quartus Prime 18 and today I couldn't compile the waveform file (.wvf) - even though I could do it before. Tried with other Quartus projects and the results are the same, any ideas? The error code I get from the flow progress is the following:

Code:

Determining the location of the ModelSim executable...
Using: c:/intelfpga_lite/18.0/modelsim_ase/win32aloem/

 To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.

 **** Generating the ModelSim Testbench ****

 quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off MISC -c MISC --vector_source="C:/Users/cufar/Documents/Universidad/ElectronicaV/Trabajos Practicos/MISC/Waveform.vwf" --testbench_file="C:/Users/cufar/Documents/Universidad/ElectronicaV/Trabajos Practicos/MISC/simulation/qsim/Waveform.vwf.vt"

 Info: *******************************************************************
 Info: Running Quartus Prime EDA Netlist Writer
    Info: Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions
    Info: and other software and tools, and its AMPP partner logic
    Info: functions, and any output files from any of the foregoing
    Info: (including device programming or simulation files), and any
    Info: associated documentation or information are expressly subject
    Info: to the terms and conditions of the Intel Program License
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Thu May 24 18:47:32 2018
 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off MISC -c MISC --vector_source="C:/Users/cufar/Documents/Universidad/ElectronicaV/Trabajos Practicos/MISC/Waveform.vwf" --testbench_file="C:/Users/cufar/Documents/Universidad/ElectronicaV/Trabajos Practicos/MISC/simulation/qsim/Waveform.vwf.vt"
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 

 Completed successfully.

 Completed successfully.

 **** Generating the functional simulation netlist ****

 quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/cufar/Documents/Universidad/ElectronicaV/Trabajos Practicos/MISC/simulation/qsim/" MISC -c MISC

 Info: *******************************************************************
 Info: Running Quartus Prime EDA Netlist Writer
    Info: Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions
    Info: and other software and tools, and its AMPP partner logic
    Info: functions, and any output files from any of the foregoing
    Info: (including device programming or simulation files), and any
    Info: associated documentation or information are expressly subject
    Info: to the terms and conditions of the Intel Program License
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Thu May 24 18:47:34 2018
 Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/cufar/Documents/Universidad/ElectronicaV/Trabajos Practicos/MISC/simulation/qsim/" MISC -c MISC
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (204019): Generated file MISC.vo in folder "C:/Users/cufar/Documents/Universidad/ElectronicaV/Trabajos Practicos/MISC/simulation/qsim//" for EDA simulation tool
 Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 4638 megabytes
    Info: Processing ended: Thu May 24 18:47:35 2018
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01
 

 Completed successfully.

 **** Generating the ModelSim .do script ****

 C:/Users/cufar/Documents/Universidad/ElectronicaV/Trabajos Practicos/MISC/simulation/qsim/MISC.do generated.

 Completed successfully.

 **** Running the ModelSim simulation ****

 c:/intelfpga_lite/18.0/modelsim_ase/win32aloem//vsim -c -do MISC.do

 Reading C:/intelFPGA_lite/18.0/modelsim_ase/tcl/vsim/pref.tcl
 

 # 10.5b
 

 

 # do MISC.do
 # ** Warning: (vlib-34) Library already exists at "work".
 

 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
 # Start time: 18:47:36 on May 24,2018
 # vlog -work work MISC.vo
 # -- Compiling module MISC
 # -- Compiling module hard_block
 #
 # Top level modules:
 #    MISC
 # End time: 18:47:36 on May 24,2018, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 

 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
 # Start time: 18:47:36 on May 24,2018
 # vlog -work work Waveform.vwf.vt
 # -- Compiling module MISC_vlg_vec_tst
 #
 # Top level modules:
 #    MISC_vlg_vec_tst
 # End time: 18:47:37 on May 24,2018, Elapsed time: 0:00:01
 # Errors: 0, Warnings: 0
 

 Errors: 1, Warnings: 0
 RPC(simulator): channel sock724 read error: (134) socket is not connected (line 804)
 ** Fatal: Kernel lost connection to front end process.
 ** Fatal: (SIGSEGV) Bad pointer access. Closing vsimk.
 ** Fatal: vsimk is exiting with code 211.
 Exit codes are defined in the "Error and Warning Messages"
 appendix of the ModelSim User's Manual.

As you see there is an error of 'socket is not connected', I'm wondering what Socket this is talking about since this is a pure software simulation.

Cyclone IV E Speed Grad and Design Issues

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Hallo

We have a test hardware with the DE0 NANO Board which has the FPGA EP4CE22F17C6. The target Fmax for our design is 50 MHz and it can be achived in the FPGA thats on the DE0 NANO board with a speed grade of 6. Now when we try to shift the design to EP4CEF17C8, where is 8 being lower in speed grade compared to 6, our restricted Fmax comes down to 40 MHz, for the same design and same setup.

Can any one explain me the fundamental difference between the two speed grades and why do i need to change the whole design setup. Because i get a message from Timequest analyzer saying that there is a long combinational path when using speed grade 6, but no message like that when using speed grade 8.

What surprises me is that from the altera website i have seen that C8 can go upto 400 Mhz and C6 upto 300 MHz. so for both of them 50 MHz would not be a problem i would guess.

how to write SDC timing constraints for an asynchronous interface

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Hi all,

Can please some one explain how I can write constraints for an asynchronous interface? The interface is between 8051 and Cyclone FPGA, the signals coming from 8051 are ALE, CE, WR, RD and an 8-bit multiplexed I/O data and address port.
This interface is same like the 8051 interfaced with external memory. The following link showing interface of 8051 with external memory

http://www.refreshnotes.com/2016/03/...terfacing.html

There is no clock input to FPGA. This interface is already working without any timing constraints.

How To Design NIOS II/e Softcore processor in SOPC Builder of Quartus II??

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I want to design a web server by which I would be able control LEDs and Send text to LCDs. For Implementation of this my querry is
1) How to design NIOS II/e on SOPC builder ......Is there any ready VHDL code for it.
2) c or assembly language design for web server intending to do controlling LEDs etc
3) Altera debug client ....from where it can be accesed. or From where I can get this software.

VHDL code for NIOS II/e soiftcore design

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Could anyone please help me with this??
I want to design a simple web server, for that how to design a nios II/e softcore processor using SOPC buider tool of Quartus II software.??

Nios - II memory alignment issue while accessing integer from non word align location

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- Using Nios-II with eclipse. While accessing integer(32 bit) form non word align location getting incorrect value as described in below example.
- Tested with eclipse version 13 and 16, both are giving same result.

- Test case :

--------------------------------------------------------------------------------
char c[10] = {0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88};
printf("int = 0x%08x", *(int*)(&c[2]));
--------------------------------------------------------------------------------
above code should print "int = 0x66554433" but getting "int = 0x44332211"

Error loading shared libraries when setting up a float license

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Hello friends,

Thanks for opening this post.

Currently, I have an issue with setting up our floating license for Quartus PRIME Pro, as well as some other licenses bundled together in a single license .dat file.

I have been mostly following Section Set Up A License in a Network License Server of this link after I downloaded the Linux version of FLEXlm from the Download Center and installed on our license server.

Now license file is in place and everything goes well, until I do `./lmgrd -c license.dat`, and it complains about `
alterad: error while loading shared libraries: libSafeString.so: cannot open shared object file: No such file or directory`. After a bit of googling, I think it's because daemon alterad is expecting some libraries from Quartus directory. However, my understanding is, license server is not supposed to install Quartus software, only the client machines do. So I am a bit confused about why alterad is looking for these libraries, and what should I do next to resolve this. Note that I do have some experience with setting up other EDA vendors' network licenses for our company (such as Mentor and Xilinx).

Log file also attached for your information.

It would be great if you could help me here. Any comments would be appreciated.

Best regards,
Taihai
Attached Files

local memory bank

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I have read best practice guide, but I am still confused.

I have optimize the local memory to 1 read and 1 write.
However, the report.html report that the"w_local" memory use 64 RAM blocks.
I know the multiply unroll 64 times, so I need to get 64 datas(64*16=1024 bits) in 1 clock,
but since the local memory optimize to 1 read and each read read 1024 bits, therefor I use only 1 RAM block not 64 RAM blocks, right?


Code:


typedef struct{
    short ff[16];
} filter_trans;

typedef struct{
    filter_trans ww[4];
} data_trans;

typedef struct{
    filter_trans ww[4];
} weight_trans;


__kernel(){


      weight_trans w_local[576];
      data_trans data_in = read_channel_intel(data_ch);
      cont control = read_channel_intel(cont_ch);


      weight_trans get_w = w_local[control.addr];

      #pragma unroll     
      for(int n=0; n<4; n++){
            winograd[n] = 0;
            #pragma unroll
            for(int j=0; j<16; j++){
                winograd[n] += get_w.ww[n].ff[j] * data_in.ww[n].ff[j];
            }
      }
}

"w_local"
Private memory: Optimal
Requested size: 73728 bytes
Implemented size: 131072 bytes
Number of banks: 1
Bank width: 1024 bits
Bank depth: 1024 words
Total replication: 1
Additional information: Requested size 73728 bytes, implemented size 131072 bytes, stall-free, 1 read and 1 write.
- See Best Practices Guide: Local Memory for more information.
Private memory implemented in on-chip block RAM.

Cyclone V SoC Devkit problems compiling Angstrom kernel

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Hello to everyone.

I’m a doctorate of the department of Electronics Engineering of the University of Modena and Reggio Emilia (Italy) and I’m working in collaboration with a company in Bologna (Italy). This company gave me an Altera Cyclone V SOC Development Kit (already used by others inside the company, but I made sure it was brought back in the factory settings depicted by the user manual).
I have to admit that I’m pretty new to Linux, and I have little knowledge about the way operating systems work (much more about how a transistor works or is made). I have followed no one course in my academic career about how to bother with operating systems compilations. I instead have a good knowledge about C language and a sufficient knowledge about assembly and matlab. And, as you will have noticed, not being a native speaker, even my English is not perfect: sorry for that.
I work on Ubuntu 14.04 LTS operating in a virtual machine (VirtualBox version 5.2.12) running on Windows 8.1 operating in my laptop; Ubuntu is updated to the latest version and also all the packages installed.

Using the included SDcard image (with Angstrom Linux) and all the factory settings the kit works just fine, with no particular trouble.

Now, in the last weeks I was slavishly following the “getting started” guides available at rocketboards.org for the 17.1 toolkit (at the time when I have started 18.0 was not yet delivered).

  • I have started with “Compiling the Hardware Design” using the 2017.10 GSRD and using the 17.1 version of Quartus, generating the system in Platform Developer. The procedure terminates correctly and all the files supposed to be generated, they are.
  • Then following the guide “Generating and Compiling the Preloader” I generate and compile the preloader and again this time it seems that all the required files have been generated correctly in the appropriate folder.
  • Next, I generate the device tree using the device tree generator (sopc2dts) adopting the following settings:

sopc2dts --input soc_system.sopcinfo\
--output socfpga.dtb\
--type dtb\
--board soc_system_board_info.xml\
--board hps_common_board_info.xml\
--bridge-removal all\
--clocks\
--verbose
And the file is generated, I suppose correctly, again, but I have read that sometimes sopc2dts can give some problems.

  • The next step is the Linux compilation, made following again the apposite guide on rocketboards.org, again in the version for the 17.1 gsrd release. I have set the host with all the packages shown in the guide; the only trouble is with ia32-libs needed since my machine is 64 bits: that package cannot be found and so cannot be installed. Then I proceed by building kernel and rootfs using angstrom 2017.10 distribution, i.e. using the following commands:

cd ~
mkdir angstrom-build
cd angstrom-build
wget http://releases.rocketboards.org/rel...src/altera.xml
wget http://commondatastorage.googleapis....downloads/repo
chmod 777 repo
export PATH=$PATH:~/angstrom-build
repo init -u git://github.com/Angstrom-distribution/angstrom-manifest -b angstrom-v2017.06-yocto2.3
mkdir -p .repo/local_manifests
mv altera.xml .repo/local_manifests/
repo sync
MACHINE=cyclone5 . ./setup-environment # Replace machine name (eg. MACHINE=cyclone5) with the target family, options are: cyclone5, arria5, arria10 and stratix10
sed -i '/meta-altera/a \ \ ${TOPDIR}\/layers\/meta-altera-refdes \\' conf/bblayers.conf # This is to add the meta-altera-refdes layer to conf/bblayers.conf
sed -i '/meta-atmel/d' conf/bblayers.conf # We do not need this layer
sed -i "s%/usr/bin/env python$%/usr/bin/env python2%" ~/bin/repo
export KERNEL_PROVIDER=linux-altera-ltsi
export KERNEL_TAG=refs/tags/ACDS17.1_REL_GSRD_UPDATE1_PR # Check above for newer release tags and replace it with the version you are building with
export UBOOT_TAG=refs/tags/ACDS17.1_REL_GSRD_UPDATE1_PR # Check above for newer release tags and replace it with the version you are building with
export KBRANCH=socfpga-4.9.78-ltsi # Check above for release branch to use
BB_ENV_EXTRAWHITE="$BB_ENV_EXTRAWHITE KBRANCH KERNEL_TAG UBOOT_TAG KERNEL_PROVIDER"

sudo bitbake gsrd-console-image
The only differences from the scripts found in the guide is the substitution of the machine name target with cyclone5, and in the line sed -i '/meta-altera/a \ \ ${TOPDIR}\/layers\/meta-altera-refdes \\' conf/bblayers.conf # This is to add the meta-altera-refdes layer to conf/bblayers.conf “layers” has replaced “sources” in the folder path since in the downloaded and extracted packet the sources folder doesn’t exist.
Now, the final report is:
NOTE: Tasks Summary: Attempted 3359 tasks of which 6 didn't need to be rerun and all succeeded.
NOTE: Writing buildhistory

Summary: There were 131 WARNING messages shown.
Of the images that should be generated, I can’t find the evidenced ones, I don’t know why.
u-boot-* U-Boot ELF file
u-boot-*.bin U-Boot binary file
u-boot-*.img U-Boot image
vmlinux Kernel ELF file
zImage Compressed kernel image
gsrd-console-image-*.cpio GSRD Root Filesystem in cpio archive format
gsrd-console-image-*.ext3 GSRD Root Filesystem as ext3 image
gsrd-console-image-*.tar.gz GSRD Root Filesystem in tar gzip archive format
gsrd-console-image-*.tar.xz GSRD Root Filesystem in tar archive format
gsrd-console-image-*.jffs2 GSRD Root Filesystem in jffs2 format
console-image-*.cpio Standard Angstrom Root Filesystem in cpio archive format
console-image-*.ext3 Standard Angstrom Root Filesystem as ext3 image
console-image-*.tar.gz Standard Angstrom Root Filesystem in tar gzip archive format
console-image-*.tar.xz Standard Angstrom Root Filesystem in tar archive format
console-image-*.jffs2 GSRD Root Filesystem in jffs2 format

  • I have created once the u-boot.scr script using the instructions in the guide “Progremming FPGA”.


Continue...

NIOS II instruction execution time

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Hi there :)

I have a question that might be a noobie one. I'm developing a test equipment on DE0 nano board in which i need to stream data over Ethernet.
In my design the ethernet tranmission is handeled by nios ii processor which send the needed data to WIZ5300 (mapped as avalon memmory mapped slave).
I'm facing problems in acheiving the required throuhput
after some investigation, although the processor is working on 140MHz clock generated from PLL. the execution of simple for loop just toggling a led takes around 2us per iteration. which i find an absolutely huge time for this clock frequency.

I'm wondering how can i know the execution time of the NIOS II instructions when coding in C (using HAL).
Is there any kind of configuration that i might be missing ?

Debug cannot enter main function when target is DDR

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Dear all,

I have some questions about the U-boot. The hardware board is designed by myself. The SoC is 10AS016E4F27E3SG.

I run the Bootloader on the board and print the following information:

U-Boot 2014.10 (May 25 2018 - 14:37:47)


CPU : Altera SOCFPGA Arria 10 Platform
BOARD : Altera SOCFPGA Arria 10 Dev Kit
I2C: ready
DRAM: WARNING: Caches not enabled
SOCFPGA DWMMC: 0
FPGA: writing socfpga.rbf ...
Full Configuration Succeeded.
DDRCAL: Success
INFO : Skip relocation as SDRAM is non secure memory
Reserving 2048 Bytes for IRQ stack at: ffe386e8
DRAM : 1 GiB
WARNING: Caches not enabled

Can I think that the DDR hardware circuit is correct? Debug can enter main function when target is onchip-ram but debug cannot enter main function when target is DDR,what should i do?
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