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ARM cache coherency

May 25, 2018, 8:48 am
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I have just joined a team of engineers working on an ARRIA 10 design with the HPS.

The FPGA fabric has several interfaces that DMA their data into the HPS DRAM via a FPGA to HPS bridge. We are seeing many issues of data corruption which I am convinced is a cache coherency problem.

I am trying to figure out exactly what sort of cache the ARM uses (write through? Write back? Snooping?) but I am just getting myself confused. I see mention of a 'system register' where the type of cache would get written. Is this programmable? Is there a standard default?

The AXI bus has the four bit field AWCACHE. It appears that the system currently designed here is setting these four bits to zero. I am not sure, but I think that is the least likely to work value. I have seen other references where all ones (4'b1111) is good. But then does the setting of that System register need to match?

Is there an Altera Reference design that has a DMA module in the FPGA fabric to the FPGA to HPS bridge that I can use as a starting point here?

Thanks

Rod

One more question: How big is a cache line on the ARM?
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Displayport : channel reconfiguration

May 25, 2018, 9:56 am
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Hi everyone,
i struggle to make the display port work on a10 sockit.
To be more precise, i use the demo given in rocketboards, so in TX mode at 5.4GBps, 1920x1080p test pattern gen II and Clocked Video output with colour bars to be displayed.
After AUX channel transactions, i can read that my TX channel has been configured like this
Quote:
------------------------------------------
------ TX Main stream attributes -----
------------------------------------------
--- Stream 0 ---
MSA lock : 1
VB-ID : 10 MISC0 : 20 MISC1 : 00
Mvid : 232F Nvid : 8000
Htotal : 2200 Vtotal : 1125
HSP : 0000 HSW : 0044
Hstart : 0192 Vstart : 0041
VSP : 0000 VSW : 0005
Hwidth : 1920 Vheight : 1080
CRC R : 22f0 CRC G : 0a2e CRC B : b7bb
--- Stream 1 ---
MSA lock : 0
VB-ID : 00 MISC0 : 00 MISC1 : 00
Mvid : 0000 Nvid : 0000
Htotal : 0000 Vtotal : 0000
HSP : 0000 HSW : 0000
Hstart : 0000 Vstart : 0000
VSP : 0000 VSW : 0000
Hwidth : 0000 Vheight : 0000
CRC R : 0000 CRC G : 0000 CRC B : 0000
------------------------------------------
-------- TX Link configuration -------
------------------------------------------
Lane count : 1
Link rate : 1620 Mbps
I don't understand why i get only one lane count. If you have an idea, please share it. Thanks
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Modelsim & VHDL Configuration

May 25, 2018, 2:18 pm
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Hi,
I have one entity in a file and several architectures in separe files.
Each architecture file have a configuration statement.

Code:
configuration CONFIGURATION_NAME of INSTANTIATING_ENTITY is 
    for INSTANTIATING_ARCH     
      for INSTANCE_NAME : COMPONENT_NAME     
          use entity LIBRARY_NAME.ENTITY_NAME(ARCHITECTURE_NAME);   
      end for; 
    end for;
end CONFIGURATION_NAME;
and I call vsim like that : vsim -novopt LIBRARY_NAME.CONFIGURATION_NAME

I wanted to speed up simulation so I removed -novopt and the design failed to be loaded.

Can you confirm Modelsim does not support configuration feature in optimized mode ? ( tried on 10.0e and 10.5c)

Best regards
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Using ALTLVDS for a TI 12-bit ADC

May 25, 2018, 2:50 pm
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Hello,

I am currently trying to latch data from an ADC that uses LVDS communication (AFE5801, http://www.ti.com/lit/ds/symlink/afe5801.pdf). I'm currently working with a Terasic DE0 Nano SoC.
This is my first time working with LVDS, so I'm looking for some advice on how to start.
I've discovered that I need to use a DDR register and serial-to-parallel shift register to accomplish this. The ALTLVDS_RX function seems to handle this for me, but I had a few questions about how to set this up:

- The ADC has a output frame clock. Is supposed to be the input clock to the ALTLVDS_RX function?
- What reason would you need to use the external PLL setting in the function?
- Since the max deserialization factor setting is 10x, I understand that I need to set the function 6x instead, and load 12bit register over two clock cycles. What exactly are the timing parameters involved with this?

Any examples of the ALTLVDS_RX function in use would be appreciated.

Thanks
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installing the USB Blaster on Windows

May 25, 2018, 11:47 pm
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Hey All,

I had been baning my head against a wall trying to install the USB blaster drivers for Windows, but I have finally found the answer after being pointed to a "solution" on Altera's web page (Which i had not found). Hopefully re posting this here will save some pain.

I was seeing the folllowing error after following the steps in the Altera User manual :- Error : The specified location does not contain information about your hardware

The basic answer was to uninstall the USB blaster driver from WIndows, Reboot, and then plug the cable back in and use the add hardware wizzard that pops up's.
(pointing it to the drivers/usb-blaster/ (x32 /x64) folder under Quartus II).

For full details search www.altera.com for "Error : The specified location does not contain information about your hardware"
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Prime Lite 17.1.0.590

May 25, 2018, 11:57 pm
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Hello, I'm trying to install the latest Quartus Prime Lite, free edition 17.1.0.590, on Ubuntu (17.10). Launching "./setup.sh" works, but at the end of the Help installation, InstallBuilder hangs. If I re-run setup.sh and omit the Help install, then at the end of ModelSIM the same happens again.

My hunch is that in both cases InstallBuilder might be running into this bug described as fixed in version "17.10.0 2017-10-30" of InstallBuilder, see: InstallBuilder not fully exiting at end of installation on some Linux environments - it looks like everything (except help) DID get installed, however.

At this point, I'm unable to get past the license step, the online connection fails - but that's a different issue, I suppose.

-jcw
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Kernel panic after 7 days, 18hours, 30minutes if VLAN is up

May 26, 2018, 11:42 am
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I always get a Kernel panic after 7 days, 18hours and 30 minutes (186 hours and half) when I have my ethernet connection with VLANs in the OS (nios2 nommu running kernel 2.6.39). If the ethernet connection is without VLAN, the system works fine.

The crash moment is not traffic dependent, but some traffic is necessary for crashing, with no traffic the crash does not happen.

The ethernet driver an adaptation of open_eth for the Altera UDP/IP Ethernet Core.

Any help is welcome.
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Nested Qsys IP

May 26, 2018, 4:47 pm
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Quartus 17.1.0 Pro

Can a custom Qsys component include a Qsys IP file? When I attempt to do this, the QSYS file is copied, but not generated. This results in the following error during Synthesis:

Error(16556): The synthesis RTL for *.qsys has not been generated. Generate the synthesis RTL from within Platform Designer.

I'm using the "add_fileset_file" TCL command to add the QSYS file, but what would the correct "type" property be? I've tried "ACCESSORY_IP" and "OTHER," but when looking at the generated QIP file, nothing seems to tag the global assignment with "QSYS_FILE." I always see MISC_FILE or SOURCE_FILE, which leads to my error message.

My current work around is to modify the generated QIP file with the proper "QSYS_FILE" tag.
Is this expected or did I miss something?

Thanks!
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Frustratiopn getting the DE0-Nano control panel to work.

May 26, 2018, 8:47 pm
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New here! Just got a DE0-Nano. Real frustration from the get go!
Cannot even get the DE0-Nano control panel to work.
I installed the Altera FPGA (free) development tool Quartu2 II Prime 18.
Its on C:\intelFPGA_lite on a Windows 10 system. Took a long time to install but no apparent problems.
After a lot of screwing around I managed to install the USB_Blaster driver. Was deep down in the above folder.
Checks out OK in windows device manager.

I then installed the DE0-Nano_ControlPanel (DE0-Nano_Controlpanel.exe) at:-
.....\Documents\FPGA\DE0-Nano
and DE0_SystemBuilder also at:-
.....\Documents\FPGA\DE0-Nano

when I go to run the DE0-Nano_ControlPanel
I get

"failed to find Quartus installation folder!"
then

then




can somebody point out what the problem is before I throw this thing in the trash can. Wasted 3 hours on it already!

Thanks in advance
John

:evil:
Attached Images
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intellectual property (IP) core filter design lisence

May 27, 2018, 7:03 pm
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Hello.

For now I use Quartus Prime Lite Edition v.18.0. But in future I want to work with Cyclone V E.
Which licence should I buy in order to operate with FIR II library from intellectual property (IP) core to do filter design?
During what time a bought licence will be active ? And how much it will cost to extend it duration?

Thanks.
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MAX10 Pinout - REFGND pin

May 27, 2018, 11:48 pm
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32-bit installer for Quartus Prime v15.1

May 27, 2018, 11:57 pm
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Hello,

I'm looking for the 32-bit version of Quartus Prime v15.1 (Lite Edition)
It seems only the 64-bit version is available from the download center.

Anyone knows where to find this ?

Thanks
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Timer

May 28, 2018, 12:42 am
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HI

Please I need ur help
I wanna print :'HELLO WORD " 100000 TIMES and then I wanna print how many time it takes

thank u
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shell commend windows _putty linux

May 28, 2018, 12:54 am
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Hi
I have question please
I transfer the file .o from shell commend windows to putty linux throught ethernet the adress IP OF the board fpga
Can I transfer the data from putty to shell commend (reverse)?
which adress I need to use ?

thank u
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arm-linux-gnueabihf-g++ command line parameter to keep asm files

May 28, 2018, 1:55 am
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Search in Google with "site:alteraforum.com" don`t get results.
I want see machine code translated with arm-linux-gnueabihf-g++ from my C to ASM.
In debugger DS-5 it is inconveniently.
Anybody see such parameter ?
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make_sdimage - Scrpt not working correctly

May 28, 2018, 2:11 am
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SOLVED:

Due to my inexperience with Ubuntu/Linux, I did not know of the symlink files. After finding the "real" files and using them I were able to create the sd-image.


Hi, I'm trying to create a sd-card from rebuilt binaries.

I've followed the GSRD tutorials on Rocketboards, but I've hit a wall. I have some issues when trying to execute the make_sdimage.py script supplied by Altera/Intel.

Here is the script call with parameters:
Code:
# sudo ./make_sdimage.py  \
  -f \
  -P preloader-mkpimage.bin,u-boot-sockit.img,num=3,format=raw,size=10M,type=A2  \
  -P rootfs/*,num=2,format=ext3,size=1500M  \
  -P zImage,u-boot.scr,soc_system.rbf,socfpga.dtb,num=1,format=vfat,size=500M  \
  -s 2G  \
  -n sd_card_image_cyclone5.bin
Here is the error output:
Code:
# info: creating the image sd_card_image_cyclone5.bin
# info: creating the partition table
# info: processing partitions...
    partition #1...
# error: failed to copy zImage

I'm running Ubuntu 16.04 LTS as a virtual image with VirtualBox.

Anyone have any ideas what might cause this?

Folder contents:
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MAX10 UFM access time

May 28, 2018, 6:41 am
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I am considering MAX10 as a device for an ongoing project, which uses soft-cpu (not NIOS). I would like to use UFM as a program storage.
I'm wondering what is access time of UFM? In the documentation (MAX10 User Flash Memory User Guide) I've found that it takes 5 clock cycles
for UFM to output valid data. Not sure if I understood it right (seems too long) - or am I missing something...?
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Reading ADC and writing to DAC from Nios C program - examples?

May 28, 2018, 1:06 pm
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Hi. First of all, thank you to Intel and Altera FPGA for the impressively extensive documentation, training lessons, and examples. :)

I am just getting started with Altera/Intel FPGA system, but I've now completed a number of the available demos, and have successfully read from buttons and controlled leds from within running NIOS2 C program, on my Max10.50 Dev. Kit.

I have added an ADC, and now need to read ADC data to a variable in the C code.

Although I have found just about everything else documented or covered in online training, nothing comes up when i search for examples that include the Eclipse code for simply reading from ADC. It would be great to know i have all the right elements and include files in place, read/write syntax, etc., to do a simple 1 channel read to variable, either from interrupt, or by loop in main until ADC is not 'busy'.

The customer training - AD conversion in the Max10 Device - https://www.altera.com/customertrain...ion_html5.html - is top notch, and comes with a very helpful video walk through, to the point where ADC vales are printed to the LCD live. They skip over the compiling and any NIOS2 code required, and go straight to the finished demo showing display values. So the part they skipped over, the code for the NIOS is what i am interested in. Is there possibly a project folder for the above training, with Eclipse project?

To summarize, i am wondering if there is C coding example (Eclipse project with .h etc.), that reads ADC value to a C variable, and or, writes a C variable to a DAC, or if anyone has an example handy to share.

Thanks,
Bob
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How to make some verilog codes invisible in a Quartus project?

May 28, 2018, 7:01 pm
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I want to protect several critical and quite difficult-designed verilog code segments in a FPGA project, based on Quartus II 15.0 platform. Unfortunately, I don't know how to make them invisible in Quartus II. May I ask help in the forum since the codes are very important in the oncoming projects ?
I'm looking forward for the reply ASAP. Thank you!
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Quartus 17.1 Retime stage internal error

May 28, 2018, 7:54 pm
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When I compile a project in 17.1, an internal error is reported in the Retime stage.

The error report as follow:
Internal Error： Sub-system: STA, File: /quartus/tsm/sta/sta_odv.cpp, Line：597
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