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Input Clock Rate Selection

May 30, 2018, 6:29 am
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What things should be considered when selecting the input clock rate for FPGAs?

Background on this question:
Previously I have used a 64MHz clock into CycloneI - IV, Cyclone10 or MAX10. Usually the internal clocks after PLL are 80MHz or 144MHz. On a recent design, some jumper wires had to be added to correct traces for the clock. Less than ideal routing caused loss of PLL lock. It then occurred to me that the clock should be much slower to ease board design. A switch was made to 8MHz, which still allowed for 80MHz and 144MHz internally. The PLL is able to stayed locked with this configuration.

Is selecting the slowest possible clock a good idea?
+This has less problems with poor board design.
+The PLL adjustment resolution is finer - might be useful if a new rate is needed later.
-More jitter?
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Unable to checkout Linux Kernel from Git

May 30, 2018, 11:21 am
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Hello,


I am configuring a Kernel on Arrow SoCkit Evaluation board with Cyclone V SoC (5CSXFC6D631C6N)
I was following the Embedded Linux Beginners guide as provide in Rocketboards.
Now, I am unable to checkout ‘rel_socfpga-4.1_15.09.01_pr’ from Altera SoCfpga repository.
Does anybody have a source for that file? Or any alternate release that I can use.


Thanks for your help.
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Verilog coding issue

May 30, 2018, 6:09 pm
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:confused::confused:Hello everyone
can some buddy guide me how initialize your own data set in verilog with complete sample example. I have written a code but getting error

module mean(A1,A2,A3,B1,B2,B3,C1,C2,C3,D1,D2,D3,M1,M2,M3) ;
input A1,A2,A3,B1,B2,B3,C1,C2,C3,D1,D2,D3;
output M1,M2,M3;
reg A1[50][1]='{51,49,47,46,50,54,46,50,44,49,54,48,48,43,58,57 ,54,51,57,51,54,51,46,51,48,50,50,52,52,47,48,54,5 2,55,49,50,55,49,44,51,50,45,44,50,51,48,51,46,53, 50};
reg A2[50][1]='{70,64,69,55,65,57,63,49,66,52,50,59,60,61,56,67 ,56,58,62,56,59,61,63,61,64,66,68,67,60,57,55,55,5 8,60,54,60,67,63,56,55,55,61,58,50,56,57,57,62,51, 57};
reg A3[50][1]='{63,58,71,63,65,76,49,73,67,72,65,64,68,57,58,64 ,65,77,77,60,69,56,77,63,67,72,62,61,64,72,74,79,6 4,63,61,77,63,64,60,69,67,69,58,68,67,67,63,65,62, 59};

reg B1[50][1]='{35,30,32,31,36,39,34,34,29,31,37,34,30,30,40,44 ,39,35,38,38,34,37,36,33,34,30,34,35,34,32,31,34,4 1,42,31,32,35,36,30,34,35,23,32,35,38,30,38,32,37, 33};
reg B2[50][1]='{32,32,31,23,28,28,33,24,29,27,20,30,22,29,29,31 ,30,27,22,25,32,28,25,28,29,30,28,30,29,26,24,24,2 7,27,30,34,31,23,30,25,26,30,26,23,27,30,29,29,25, 28};
reg B3[50][1]='{33,27,30,29,30,30,25,29,25,36,32,27,30,25,28,32 ,30,38,26,22,32,28,28,27,33,32,28,30,28,30,28,38,2 8,28,26,30,34,31,30,31,31,31,27,32,33,30,25,30,34, 30};
reg C1[50][1]='{14,14,13,15,14,17,14,15,14,15,15,16,14,11,12,15 ,13,14,17,15,17,15,10,17,19,16,16,15,14,16,16,15,1 5,14,15,12,13,14,13,15,13,13,13,16,19,14,16,14,15, 14};
reg C2[50][1]='{47,45,49,40,46,45,47,33,46,39,35,42,40,47,36,44 ,45,41,45,39,48,40,49,47,43,44,48,50,45,35,38,37,3 9,51,45,45,47,44,41,40,44,46,40,33,42,42,42,43,30, 41};
reg C3[50][1]='{60,51,59,56,58,66,45,63,58,61,51,53,55,50,51,53 ,55,67,69,50,57,49,67,49,57,60,48,49,56,58,61,64,5 6,51,56,61,56,55,48,54,56,51,51,59,57,52,50,52,54, 51};
reg D1[50][1]='{02,02,02,02,02,04,03,02,02,01,02,02,01,01,02,04 ,04,03,03,03,02,04,02,05,02,02,04,02,02,02,02,04,0 1,02,02,02,02,01,02,02,03,03,02,06,04,03,02,02,02, 02};
reg D2[50][1]='{14,15,15,13,15,13,16,10,13,14,10,15,10,14,13,14 ,15,10,15,11,18,13,15,12,13,14,14,17,15,10,11,10,1 2,16,15,16,15,13,13,13,12,14,12,10,13,12,13,13,11, 13};
reg D3[50][1]='{25,19,21,18,22,21,17,18,18,25,20,19,21,20,24,23 ,18,22,23,15,23,20,20,18,21,18,18,18,21,16,19,20,2 2,15,14,23,24,18,18,21,24,23,19,23,25,23,19,20,23, 18};
endmodule
:confused:
thanks in advance
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Frustratiopn getting the DE0-Nano control panel to work.

May 26, 2018, 8:47 pm
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New here! Just got a DE0-Nano. Real frustration from the get go!
Cannot even get the DE0-Nano control panel to work.
I installed the Altera FPGA (free) development tool Quartu2 II Prime 18.
Its on C:\intelFPGA_lite on a Windows 10 system. Took a long time to install but no apparent problems.
After a lot of screwing around I managed to install the USB_Blaster driver. Was deep down in the above folder.
Checks out OK in windows device manager.

I then installed the DE0-Nano_ControlPanel (DE0-Nano_Controlpanel.exe) at:-
.....\Documents\FPGA\DE0-Nano
and DE0_SystemBuilder also at:-
.....\Documents\FPGA\DE0-Nano

when I go to run the DE0-Nano_ControlPanel
I get

"failed to find Quartus installation folder!"
then

then




can somebody point out what the problem is before I throw this thing in the trash can. Wasted 3 hours on it already!

Thanks in advance
John

:evil:
Attached Images
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intellectual property (IP) core filter design lisence

May 27, 2018, 7:03 pm
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Hello.

For now I use Quartus Prime Lite Edition v.18.0. But in future I want to work with Cyclone V E.
Which licence should I buy in order to operate with FIR II library from intellectual property (IP) core to do filter design?
During what time a bought licence will be active ? And how much it will cost to extend it duration?

Thanks.
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MAX10 Pinout - REFGND pin

May 27, 2018, 11:48 pm
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32-bit installer for Quartus Prime v15.1

May 27, 2018, 11:57 pm
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Hello,

I'm looking for the 32-bit version of Quartus Prime v15.1 (Lite Edition)
It seems only the 64-bit version is available from the download center.

Anyone knows where to find this ?

Thanks
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Timer

May 28, 2018, 12:42 am
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HI

Please I need ur help
I wanna print :'HELLO WORD " 100000 TIMES and then I wanna print how many time it takes

thank u
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shell commend windows _putty linux

May 28, 2018, 12:54 am
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Hi
I have question please
I transfer the file .o from shell commend windows to putty linux throught ethernet the adress IP OF the board fpga
Can I transfer the data from putty to shell commend (reverse)?
which adress I need to use ?

thank u
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arm-linux-gnueabihf-g++ command line parameter to keep asm files

May 28, 2018, 1:55 am
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Search in Google with "site:alteraforum.com" don`t get results.
I want see machine code translated with arm-linux-gnueabihf-g++ from my C to ASM.
In debugger DS-5 it is inconveniently.
Anybody see such parameter ?
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make_sdimage - Scrpt not working correctly

May 28, 2018, 2:11 am
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SOLVED:

Due to my inexperience with Ubuntu/Linux, I did not know of the symlink files. After finding the "real" files and using them I were able to create the sd-image.


Hi, I'm trying to create a sd-card from rebuilt binaries.

I've followed the GSRD tutorials on Rocketboards, but I've hit a wall. I have some issues when trying to execute the make_sdimage.py script supplied by Altera/Intel.

Here is the script call with parameters:
Code:
# sudo ./make_sdimage.py  \
  -f \
  -P preloader-mkpimage.bin,u-boot-sockit.img,num=3,format=raw,size=10M,type=A2  \
  -P rootfs/*,num=2,format=ext3,size=1500M  \
  -P zImage,u-boot.scr,soc_system.rbf,socfpga.dtb,num=1,format=vfat,size=500M  \
  -s 2G  \
  -n sd_card_image_cyclone5.bin
Here is the error output:
Code:
# info: creating the image sd_card_image_cyclone5.bin
# info: creating the partition table
# info: processing partitions...
    partition #1...
# error: failed to copy zImage

I'm running Ubuntu 16.04 LTS as a virtual image with VirtualBox.

Anyone have any ideas what might cause this?

Folder contents:
Attached Images
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MAX10 UFM access time

May 28, 2018, 6:41 am
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I am considering MAX10 as a device for an ongoing project, which uses soft-cpu (not NIOS). I would like to use UFM as a program storage.
I'm wondering what is access time of UFM? In the documentation (MAX10 User Flash Memory User Guide) I've found that it takes 5 clock cycles
for UFM to output valid data. Not sure if I understood it right (seems too long) - or am I missing something...?
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Reading ADC and writing to DAC from Nios C program - examples?

May 28, 2018, 1:06 pm
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Hi. First of all, thank you to Intel and Altera FPGA for the impressively extensive documentation, training lessons, and examples. :)

I am just getting started with Altera/Intel FPGA system, but I've now completed a number of the available demos, and have successfully read from buttons and controlled leds from within running NIOS2 C program, on my Max10.50 Dev. Kit.

I have added an ADC, and now need to read ADC data to a variable in the C code.

Although I have found just about everything else documented or covered in online training, nothing comes up when i search for examples that include the Eclipse code for simply reading from ADC. It would be great to know i have all the right elements and include files in place, read/write syntax, etc., to do a simple 1 channel read to variable, either from interrupt, or by loop in main until ADC is not 'busy'.

The customer training - AD conversion in the Max10 Device - https://www.altera.com/customertrain...ion_html5.html - is top notch, and comes with a very helpful video walk through, to the point where ADC vales are printed to the LCD live. They skip over the compiling and any NIOS2 code required, and go straight to the finished demo showing display values. So the part they skipped over, the code for the NIOS is what i am interested in. Is there possibly a project folder for the above training, with Eclipse project?

To summarize, i am wondering if there is C coding example (Eclipse project with .h etc.), that reads ADC value to a C variable, and or, writes a C variable to a DAC, or if anyone has an example handy to share.

Thanks,
Bob
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Unknown IDCODE for Cyclone 10GX device

May 28, 2018, 4:37 pm
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Greetings. I am doing board bring-up on a new design that uses a Cyclone 10GX (PN: 10CX105YF672E5G). When I execute a AutoDetect in the Quartus Pro programmer it reports UNKNOWN_2E720DD. The C10GX handbook chapter9 page 240 shows that 02E20DD is the correct IDCODE for the GX105. I ran the JTAG Chain Debugger IDCODE Iteration Test several hundred iterations and it reported that "JTAG chain connection is good and consistent". I was using Quartus Pro 17.1 and updated to 18.0 and get the same unknown ID.

I made a simple project that passed a clock signal to an output test point. The sof loaded ok through the JTAG (programmer GUI reported success), CONFIG_DONE went high (always a good thing), and my clock showed up at the test point. So the board is behaving at some basic level.

I added a NIOS processor and had it toggle an output pin in a forever loop. However I could not connect through the Eclipse NIOS debugger nor the System Console (System Console reports 02E720DD@1 connected to the USB-BlasterII). I added Signal Tap to the project but it reports device "@1: (0x02E720DD)" when I execute the Scan Chain button.

It seems that Quartus just does not recognize the ID which looks correct. Does anyone have a suggestion how this can be overridden? Or is the problem really on my end?
Thanks,
Bill
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How to make some verilog codes invisible in a Quartus project?

May 28, 2018, 7:01 pm
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I want to protect several critical and quite difficult-designed verilog code segments in a FPGA project, based on Quartus II 15.0 platform. Unfortunately, I don't know how to make them invisible in Quartus II. May I ask help in the forum since the codes are very important in the oncoming projects ?
I'm looking forward for the reply ASAP. Thank you!
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Quartus 17.1 Retime stage internal error

May 28, 2018, 7:54 pm
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When I compile a project in 17.1, an internal error is reported in the Retime stage.

The error report as follow:
Internal Error： Sub-system: STA, File: /quartus/tsm/sta/sta_odv.cpp, Line：597
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Hps_fpga

May 28, 2018, 10:36 pm
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PLEEASE I need help
How can I build a timer using fpga/HPS in order to print the delay of runing the task.in putty .
This is my first experimce using HPS /C program

Thank u
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Contact Sales Representatives for purchasing IP Licenses

May 29, 2018, 10:58 am
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Hi all,

I am using Quartus Prime Lite version (do not own a standard or pro version), and in the need of purchasing DDR2 SDRAM controller IP from Altera (the one available from the IP base suite).

On all the information I can find online (Altera site), I was told to contact their sales representatives (and IP are not available for online purchase).
I browsed to their list of sales representatives in north America (I live in BC, Canada), only to find it empty. I contacted Arrow, one of their authorized distributor for parts,
and they told me they need a product code, which does not seem to be available anywhere.

I have contacted Altera Telesales group and sales support offices in Ottowa, with no replies.

Will anyone share their experience speaking to a sales representative or provide some contacts relating to this issue?

Thanks for your attention.

Ben Chang
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fpll to fpll cascading with Arria10 transceivers

May 30, 2018, 3:01 am
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Hi,

I'm having trouble getting a working Arria10 transceiver configuration. Due to a kind of design flaw on my board I have a 240 MHz reference clock and I need a 160 MHz reference clock. I'm trying to use fPLL to fPLL cascading.
The setup is currently like this:

input 240 MHz -> cascading fPLL -> 160 MHz -> transceiver fPLL -> 2560 MHz serial transceiver clock

The 160 MHz clock is also used for the CDR reference.

I have an Avalon Memory Map to recalibrate the fPLLs (particularly the second one). However, when I talk to the first fPLL I always get back state 0x84 (from any subaddress). Does anyone have any experience with this kind of setup?

I can provide more info and the project files if necessary.

Advance thanks,
Karol.
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Input Clock Rate Selection

May 30, 2018, 6:29 am
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What things should be considered when selecting the input clock rate for FPGAs?

Background on this question:
Previously I have used a 64MHz clock into CycloneI - IV, Cyclone10 or MAX10. Usually the internal clocks after PLL are 80MHz or 144MHz. On a recent design, some jumper wires had to be added to correct traces for the clock. Less than ideal routing caused loss of PLL lock. It then occurred to me that the clock should be much slower to ease board design. A switch was made to 8MHz, which still allowed for 80MHz and 144MHz internally. The PLL is able to stayed locked with this configuration.

Is selecting the slowest possible clock a good idea?
+This has less problems with poor board design.
+The PLL adjustment resolution is finer - might be useful if a new rate is needed later.
-More jitter?
↧
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