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Unable to checkout Linux Kernel from Git

May 30, 2018, 11:21 am
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Hello,


I am configuring a Kernel on Arrow SoCkit Evaluation board with Cyclone V SoC (5CSXFC6D631C6N)
I was following the Embedded Linux Beginners guide as provide in Rocketboards.
Now, I am unable to checkout ‘rel_socfpga-4.1_15.09.01_pr’ from Altera SoCfpga repository.
Does anybody have a source for that file? Or any alternate release that I can use.


Thanks for your help.
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DDR2 Controller Lock Up Mid Read Operation

May 30, 2018, 3:12 pm
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We are implementing a DDR2 interface using the avalon MM master templates provided by Altera. The issue is that on occasion, we will assert a read request to the avalon read master and the read process never finishes. Using SignalTap to debug it was determined that the read master has begun to read data out from the DDR2 but does not finish. The issue is that the "waitrequest" signal goes high during the read, and is never deasserted, causing a lockup. I would like any insight for this issue you can give me. We have been trying to debug this for a long time and the deadline to get this working is very soon. The interface width is 32 bits on each side, it is made sure that all write and read lengths/addresses are on a 4 byte boundary. It is made sure that the length and address signals are held stable multiple cycles before the "go" signal is asserted. It is made sure that the FIFO is empty at the beginning of a read. It is made sure the address is not exceeding the memory limit or bit width. The board is a custom board, with routing rules being adhered to for the ddr2 lines (impedance controlled/length matched). Is there any idea what might be causing this? What seems to significantly reduce the probability of this happening is to disable "force burst alignment". Enabling/disabling burst seems to also alter this probability, but nothing we have tried so far completely alleviates the situation. Does anyone have any insights? I can provide my source code and setup in a limited fashion if necessary.
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Verilog coding issue

May 30, 2018, 6:09 pm
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:confused::confused:Hello everyone
can some buddy guide me how initialize your own data set in verilog with complete sample example. I have written a code but getting error

module mean(A1,A2,A3,B1,B2,B3,C1,C2,C3,D1,D2,D3,M1,M2,M3) ;
input A1,A2,A3,B1,B2,B3,C1,C2,C3,D1,D2,D3;
output M1,M2,M3;
reg A1[50][1]='{51,49,47,46,50,54,46,50,44,49,54,48,48,43,58,57 ,54,51,57,51,54,51,46,51,48,50,50,52,52,47,48,54,5 2,55,49,50,55,49,44,51,50,45,44,50,51,48,51,46,53, 50};
reg A2[50][1]='{70,64,69,55,65,57,63,49,66,52,50,59,60,61,56,67 ,56,58,62,56,59,61,63,61,64,66,68,67,60,57,55,55,5 8,60,54,60,67,63,56,55,55,61,58,50,56,57,57,62,51, 57};
reg A3[50][1]='{63,58,71,63,65,76,49,73,67,72,65,64,68,57,58,64 ,65,77,77,60,69,56,77,63,67,72,62,61,64,72,74,79,6 4,63,61,77,63,64,60,69,67,69,58,68,67,67,63,65,62, 59};

reg B1[50][1]='{35,30,32,31,36,39,34,34,29,31,37,34,30,30,40,44 ,39,35,38,38,34,37,36,33,34,30,34,35,34,32,31,34,4 1,42,31,32,35,36,30,34,35,23,32,35,38,30,38,32,37, 33};
reg B2[50][1]='{32,32,31,23,28,28,33,24,29,27,20,30,22,29,29,31 ,30,27,22,25,32,28,25,28,29,30,28,30,29,26,24,24,2 7,27,30,34,31,23,30,25,26,30,26,23,27,30,29,29,25, 28};
reg B3[50][1]='{33,27,30,29,30,30,25,29,25,36,32,27,30,25,28,32 ,30,38,26,22,32,28,28,27,33,32,28,30,28,30,28,38,2 8,28,26,30,34,31,30,31,31,31,27,32,33,30,25,30,34, 30};
reg C1[50][1]='{14,14,13,15,14,17,14,15,14,15,15,16,14,11,12,15 ,13,14,17,15,17,15,10,17,19,16,16,15,14,16,16,15,1 5,14,15,12,13,14,13,15,13,13,13,16,19,14,16,14,15, 14};
reg C2[50][1]='{47,45,49,40,46,45,47,33,46,39,35,42,40,47,36,44 ,45,41,45,39,48,40,49,47,43,44,48,50,45,35,38,37,3 9,51,45,45,47,44,41,40,44,46,40,33,42,42,42,43,30, 41};
reg C3[50][1]='{60,51,59,56,58,66,45,63,58,61,51,53,55,50,51,53 ,55,67,69,50,57,49,67,49,57,60,48,49,56,58,61,64,5 6,51,56,61,56,55,48,54,56,51,51,59,57,52,50,52,54, 51};
reg D1[50][1]='{02,02,02,02,02,04,03,02,02,01,02,02,01,01,02,04 ,04,03,03,03,02,04,02,05,02,02,04,02,02,02,02,04,0 1,02,02,02,02,01,02,02,03,03,02,06,04,03,02,02,02, 02};
reg D2[50][1]='{14,15,15,13,15,13,16,10,13,14,10,15,10,14,13,14 ,15,10,15,11,18,13,15,12,13,14,14,17,15,10,11,10,1 2,16,15,16,15,13,13,13,12,14,12,10,13,12,13,13,11, 13};
reg D3[50][1]='{25,19,21,18,22,21,17,18,18,25,20,19,21,20,24,23 ,18,22,23,15,23,20,20,18,21,18,18,18,21,16,19,20,2 2,15,14,23,24,18,18,21,24,23,19,23,25,23,19,20,23, 18};
endmodule
:confused:
thanks in advance
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Using HPS DMAC at uboot in order to load FPGA faster

May 29, 2018, 11:36 pm
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Hello,

In our design(Arria 10, hps boot first) we are using uboot to load the FPGA from the QSPI flash. We are working with combined rbf file and the loading process takes us about 1.7 seconds.

The uboot load it by follow steps:

1. Read blocks (4k each time) from the qspi flash to internal RAM
2., Write the the block from internal RAM to fpga

In order to improve the loading time(it is very important to us), we were suggested to use the HPS DMAC instead to do it, this way theoretically all the data will be transferred from qspi flash to FPGA Manager by DMA instead of using the software and internal ram that adds the overhead.

I search for information in documentation, forums and also consulted with Elhanan Sharon, from Intel PSG department - Eastronics. As I understood, the DMAC is software controlled DMA, and in order to load the FPGA manager from the QSPI flash, specific code should be written.

Can you please answer me 2 questions:

1. Can you please give me an example how to load the fpga manager from the QSPI flash with DMAC?
2. Can you please estimate how much time will be reduced(if any) by using the DMAC instead of current implementation of copying the data through internal RAM by uboot?

Please add the Elhanan Sharon elhanan.sharon@easx.co.il at CC in the response

Thanks in advance and Best Regards,
Alex
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Fake FPGA chips - or not?

May 31, 2018, 12:13 am
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Recently I have bought several Cyclone III chips, and before soldering them, noticed that new chips are different from those I was buying for almost a decade.

Here's the pic attached. New FPGA is to the left, old FPGA is to the right. New one's year of production seems to be 2017, old one's is 2015.

I have suspended the production, and created a support request #11406605 to the Altera (now Intel) asking them two simple things:

1. May it happen that new chip I bought a counterfeit as it differs with old one?
2. Where's the pin 1 of the new chip?

Now in detail.

Chips differ slightly in two major aspects. It seems that the
- material body of chips are made of differs, leading to change of how text looks like on the body. Old chips were having brighter color of the engraving, and new chip having more reddish color of the engraving (and thus plastic it is made of);
- font used, the biggest difference is in "III" text, and it is more or less seen on the pic.

The biggest issue, which made me stuck. I would be able to tolerate the font and body color difference (which I noticed after I focused on this issue) - but the second technological grooving is NOT documented in the manuals. Current image per specification (attached) has no clue about ALTERA text on the body and has only one grooving identifying pin 1. You can say I am paranoid, and that old chip is having ALTERA logo, and pin 1 at the left top corner of it, and that new one must follow the same rule.

But I say that while chip image is out of specified in the documentation, this rule may simple change, and, with some even minor probability such assumption may be wrong. I can not allow myself tolerate this even minor probability as it will lead to a loss of specific amount of time, money and material.

Today is the 3rd day I wait for response from Altera (Intel). Not sure if questions I asked are too complicated, stupid, or hard ot tricky. But manufacturing is on hold.

I decided to perform my own investigation, and found out that some time ago, between these 15 and 17 years, Altera changed manufacturing fab from TSMC to Intel, and this may be the reason for the change of physical properties of the chip - plastic body material, font, and additional confusing grooves on the chip's body.

I want to get definite answers to the questions I asked, and changes being documented properly.
Attached Images
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Arria 10 Clock Input - Differential POD 1.2V I/O Standard

May 31, 2018, 12:45 am
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We are currently using an Arria 10 SX 270 F34 device for a project, and due to a limited number of I/O banks I want to use a spare differential pair on one of the DDR4 I/O banks as a clock input to an IOPLL.

However, as the DDR bank is stuck at 1.2V, I have been trying to find a way to connect an LVDS signal to a 1.2V I/O bank. We are using a dev-kit, so it's not possible to add an external termination resistor close to the FPGA I/O pins, limiting the options to the four I/O standards that the A10 supports internal termination four - HSTL12, SSTL12, HSUL12 and Differential POD12.

I've worked out that using an LVDS to CML converter, it should be possible to use the differential POD12 I/O standard with 48Ohm Rt and a VCCIO of 1.2V. As such, I've made the following IO assignments:

Code:
set_location_assignment PIN_AD10 -to refclk_in
set_location_assignment PIN_AD11 -to "refclk_in(n)"
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to refclk_in
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 48 OHM WITH CALIBRATION" -to refclk_in
However, when I try to compile the design in Quartus 17.1, I get the following error:

Code:
Error (18314): I/O pin refclk_in is driving a ref clock and has a pseudo-differential I/O standard. Try setting the I/O standard to a true differential I/O Standard
Error (18314): I/O pin refclk_in(n) is driving a ref clock and has a pseudo-differential I/O standard. Try setting the I/O standard to a true differential I/O Standard
I'm now confused as to what Quartus is complaining about? I am using a true differential I/O standard according to the datasheet:

Quote:
5.5.5.2.1. Differential HSTL, SSTL, HSUL, and POD Termination
  • Differential HSTL, SSTL, HSUL, and POD inputs use LVDS differential input buffers. However, RD support is only available if the I/O standard is LVDS.
  • Differential HSTL, SSTL, HSUL, and POD outputs are not true differential outputs. These I/O standards use two single-ended outputs with the second output programmed as inverted.
I'm using them as differential inputs, which apparently use LVDS differential input buffers. So surely they are true differential I/O?
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Fixed Point and DSP Usage

May 31, 2018, 2:20 am
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Hi, everyone.
Referring to code below, I am trying to implement fixed point arithmetic to replace floating point arithmetic for my application.

Surprisingly, the DSP usage increases tremendously(around 100%) from 30(floating point) to 64 (fixed point). However, all other resources: ram, logic and etc is reduced.

Code:
// Note variable A & B is 16 bit short, passed as argument from host
int sum;
short C;

for loop
    sum += A[i] + B[i];
end

C = 0xffff & (sum >> 8);
Regarding to the report, i have few doubts:
  1. Does Fixed Point arithmetic helps to reduce the DSP usage?Because, as far as i know, dsp block only consumed by floating point operation(please correct me if i'm wrong)


  1. Am I doing the fixed point in a correct way ?


  1. And what approach I can take to further reduce the DSP usage?
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QSYS with Subsystems Project Archive Problem

May 31, 2018, 6:12 am
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Hi, I am building a heirachical design in QSYS using Quartus 15.1.2 on opensuze.

I have created a qsys top system and using the "Add a new subsystem to the current system" qsys gui/tool created subsystems. The tool is working, I can drill into each subsystem and edit it and when I generate the qsys everything is functional.

The problem I am having is when I create an archive of the project using Project Archive and restore the project to a new directory, when I open qsys the subsystems are "not found or could not be instantiated". In the original project I see the subsystems in the System drop down in the IP Catalog but in the restored project they are no longer visible.

I have added the .qip files for each subsystems to my project directory and have tried adding all the files I can find to the archive process but I still end up in the same place when I restore the archive. I attempted the export as .tcl for each subsystem but after that I could not drill down into each of the subsystems to edit them.

If I generate a seperate system using qsys and import that into my top qsys as a subsystem it correctly archives but I cant see any difference in the files generated that would cause the seperate qsys files combined to work when creating the subsystems in qsys does not work.

Ideally I dont want to have to regenerate all of my subsystems as individual qsys systems and regenerate my top unless it is really necessary.

I can re-create this in a simple seperate test project.

Has anyone run into this before? Is this a bug in qsys? I cant find any similar issues on the forum or on the knowledge base.

Any help is appreciated.

Thanks,
James
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Error 10476

May 31, 2018, 8:37 am
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In this code at the time of compilation a 10476 error shows up. The code is:

-- convertidor BCD a 7 segmentos
library ieee;
use ieee.std_logic_1164.all;

-- definicion de la entidad

entity convertidor7 is
port (A: in std_logic_vector (1 downto 0);
B: in std_logic_vector (1 downto 0);
C: in std_logic_vector (1 downto 0);
D: in std_logic_vector (1 downto 0);
adisplay,bdisplay,cdisplay,ddisplay,edisplay,fdisp lay,gdisplay: out std_logic);
end convertidor7;

-- definicion de las señales de entrada / salida

architecture bolean of convertidor7 is
signal An,Bn,Cn,Dn,anda1_out,anda2_out,anda3_out,anda4_ou t,andb1_out,andb2_out,andb3_out,andb4_out,
andc1_out,andc2_out,andc3_out,andc4_out,andd1_out, andd2_out,andd3_out,andd4_out,andd5_out,
ande1_out,ande2_out,andf1_out,andf2_out,andf3_out, andf4_out,andg1_out,andg2_out,andg3_out,andg4_out: std_logic;

-- fin de definicion de las señales
-- inicio de programa principal

begin

An <= not A(1);
Bn <= not B(1);
Cn <= not C(1);
Dn <= not D(1);

-- a

anda1_out <= C and An; <=== this is the error
anda2_out <= An and B and D;
anda3_out <= Bn and Cn and Dn;
anda4_out <= A and Bn and Cn;

adisplay <= anda1_out or anda2_out or anda3_out or anda4_out;

-- b

andb1_out <= An and Bn;
andb2_out <= An and Cn and Dn;
andb3_out <= An and C and D;
andb4_out <= A and Bn and Cn;

bdisplay <=andb1_out or andb2_out or andb3_out or andb4_out;

-- c

andc1_out <= An and B;
andc2_out <= An and D;
andc3_out <= Bn and Cn and Dn;
andc4_out <= A and Bn and Cn;

cdisplay <= andc1_out or andc2_out or andc3_out or andc4_out,

-- d

andd1_out <= An and C and Dn,
andd2_out <= An and Bn and C;
andd3_out <= Bn and Cn and Dn;
andd4_out <= A and Bn and Cn;
andd5_out <= An and B and Cn and D;

ddisplay <= andd1_out or andd2_out or andd3_out or andd4_out or andd5_out;

-- e

ande1_out <= An and C and Dn;
ande2_out <= Bn and Cn and Dn;

edisplay <= ande1_out or ande2_out;

-- f

andf1_out <= An and B and Cn;
andf2_out <= An and Cn and Dn;
andf3_out <= An and B and Dn;
andf4_out <= A and Bn and Cn;

fdisplay <= andf1_out or andf2_out or andf3_out or andf4_out;

-- g

andg1_out <= An and C and Dn;
andg2_out <= An and Bn and C;
andg3_out <= An and B and Cn;
andg4_out <= A and Bn and Cn;

gdisplay <= andg1_out or andg2_out or andg3_out or andg4_out;

end bolean;

The error states:

Error (10476): VHDL error at BCD7SEG.vhd(34): type of identifier "C" does not agree with its usage as "std_ulogic" type


Could anybody help me? A do not see why

Thanks
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LPM RAM FLEX10K waveforms

May 31, 2018, 8:53 am
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Hi,
I am looking for a data sheet / apps note that shows the expected waveforms for LPM RAM DQ with registered input and an unregistered output. Could you let me know where I can find one?
Thanks
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error 10327

May 31, 2018, 10:32 am
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In this code at the time of compilation a 10327 error shows up. The code is:

- convertidor BCD a7 segmentos
library ieee;
useieee.std_logic_1164.all;


-- definicion de laentidad


entity convertidor7is
port (A: instd_logic;
B: in std_logic;
C: in std_logic;
D: in std_logic;
adisplay,bdisplay,cdisplay,ddisplay,edisplay,fdisp lay,gdisplay:out std_logic);
end convertidor7;


-- definicion de lasseñales de entrada / salida


architecture boleanof convertidor7 is
signalAn,Bn,Cn,Dn,anda1_out,anda2_out,anda3_out,an da4_out,andb1_out,andb2_out,andb3_out,andb4_out,
andc1_out,andc2_out,andc3_out,andc4_out,andd1_out, andd2_out,andd3_out,andd4_out,andd5_out,
ande1_out,ande2_out,andf1_out,andf2_out,andf3_out, andf4_out,andg1_out,andg2_out,andg3_out,andg4_out: std_logic;

-- fin de definicionde las señales
-- inicio deprograma principal


begin

An <= not A;
Bn <= not B;
Cn <= not C;
Dn <= not D;



-- a

anda1_out <= Cand An;
anda2_out <= Anand B and D;
anda3_out <= Bnand Cn and Dn;
anda4_out <= Aand Bn and Cn;

adisplay <=anda1_out or anda2_out or anda3_out or anda4_out;



-- b

andb1_out <= Anand Bn;
andb2_out <= Anand Cn and Dn;
andb3_out <= Anand C and D;
andb4_out <= Aand Bn and Cn;

bdisplay<=andb1_out or andb2_out or andb3_out or andb4_out;

-- c


andc1_out <= Anand B;
andc2_out <= Anand D;
andc3_out <= Bnand Cn and Dn;
andc4_out <= Aand Bn and Cn;

cdisplay <=andc1_out or andc2_out or andc3_out or andc4_out,

-- d


andd1_out<= An and C and Dn; --- here is the error
andd2_out <= Anand Bn and C;
andd3_out <= Bnand Cn and Dn;
andd4_out <= Aand Bn and Cn;
andd5_out <= Anand B and Cn and D;

ddisplay <=andd1_out or andd2_out or andd3_out or andd4_out or andd5_out;

-- e

ande1_out <= Anand C and Dn;
ande2_out <= Bnand Cn and Dn;


edisplay <=ande1_out or ande2_out;

-- f


andf1_out <= Anand B and Cn;
andf2_out <= Anand Cn and Dn;
andf3_out <= Anand B and Dn;
andf4_out <= Aand Bn and Cn;

fdisplay <=andf1_out or andf2_out or andf3_out or andf4_out;

-- g


andg1_out <= Anand C and Dn;
andg2_out <= Anand Bn and C;
andg3_out <= Anand B and Cn;
andg4_out <= Aand Bn and Cn;

gdisplay <=andg1_out or andg2_out or andg3_out or andg4_out;

end bolean;

the error states:



Error(10327): VHDL error at BCD7SEG.vhd(61): can't determine definition ofoperator ""<="" -- found 0 possibledefinitions

Could anybody help me? A do not see why

Thanks
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Help with a VHDL code - using an array

May 31, 2018, 1:26 pm
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Hello!

I want to use an array in order to check if my coordinates are correct, according to certain conditions. The coordinates represent a beginning point of a picture I will print on the screen using VGA and I want to duplicate this picture, I need to check if the coordinates (which I receive from a random numbers generator component) do not overlap.

I tried to make an array and fill it according to the conditions, but after running simulations on my VHDL code I noticed that the output does not receive the values from my array, even though I assign them into the output.

My code:

Quote:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;


entity pigsCoordinate is
port (
clk : in std_logic;
resetN : in std_logic;
limit : in integer;
run : in std_logic;
random : in std_logic_vector(7 downto 0);
coordinate : out integer
);
end pigsCoordinate;


architecture pigsCoordinateArch of pigsCoordinate is
type pigsArray is array (0 to 7) of integer range 0 to limit;
signal pigsArray_signal: pigsArray := (0,0,0,0,0,0,0,0);

signal counter : integer := 0;
signal counterData : integer := 0;

begin
process (clk,resetN)
variable tempLocation: integer := 0;
begin
if (resetN = '0') then
coordinate <= 0;

elsif rising_edge(clk) then
if (run = '1') then
tempLocation := conv_integer(random);

if (counter = 0) then
pigsArray_signal(counter) <= tempLocation;
counter <= counter + 1;

elsif (counter < 8) then
pigsArray_signal(counter) <= tempLocation;
for checkCounter in 0 to 7 loop
exit when ((pigsArray_signal(counter) > pigsArray_signal(checkCounter)) and
(pigsArray_signal(counter) < (pigsArray_signal(checkCounter) + 26) and
(counter /= checkCounter)));
end loop;
counter <= counter + 1;

elsif (counter = 8) and (counterData < 8) then
coordinate <= pigsArray_signal(counterData);
counterData <= counterData + 1;
end if;
end if;

end if;

end process;
end pigsCoordinateArch;
Thank you very much for your help and attention!
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Regarding the documentation on 'disabling' dev board drivers

May 31, 2018, 1:40 pm
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I recently read in the on-site documentation somewhere, that if USB-Blaster drivers are not working properly, the solution is to 'disable' the drivers. That's the end of the documented solution. Does it follow that, i would then connect the dev. board and install manually when new hardware is found? I guess that's a windows centric question. Thanks. I'm trying to resurrect a Terasic Development board.

Cheers, :)
Bob
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Cyclone V GT Avalon-MM DMA Reference Design Read/Write Timeout

May 31, 2018, 5:19 pm
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Hello, I am struggling to determine what is wrong with my Cyclone V GT setup here. When I run the software provided with the example, every read/write seems to time out upon inspection with dmesg.

To summarize, I'm running Ubuntu 16.04 with Quartus version 18.0.

I'm running the example provided at https://cloud.altera.com/devstore/pl...ternal-memory/

I downloaded the project, successfully used the ip upgrade tool, successfully compiled, and used USB Blaster II to write the .sof file to the board. The board shows up with an lspci and after managing to get the driver to compile, I ran it in terminal successfully. However, this is where I start to encounter issues.


I run it with sudo ./run and get the correct terminal menu. However, when I run option "8) loop dma", the software crashes. A relevant portion of the output from dmesg is in dmesg.txt. (UPDATE: probably should look at dmesg2.txt in the following post instead).

When I run option "8) loop dma" or option "1) start DMA" with any number of dwords or any combination of reads, writes, and simultaneous, the output of dmesg is pretty much the same as:

[ 3935.988482] Read DMA times out
[ 3935.988484] DWORD = 00000200
[ 3935.988485] Desc = 00000080
[ 3936.151718] Write DMA times out
[ 3936.151719] DWORD = 00000200
[ 3936.151720] Desc = 00000080
[ 3936.332928] Simultaneous DMA times out
[ 3936.332928] DWORD = 00000200
[ 3936.332929] Desc = 00000080


but no error or indication of anything wrong happens outside dmesg from option 1). It updates "Read Time," "Read Throughput," etc. with different values.


One other thing that I find confusing is the verbose output from lspci. Here it is:

$lspci -v | grep Altera -A 5
01:00.0 Non-VGA unclassified device: Altera Corporation Device e003 (rev ff) (prog-if ff)
!!! Unknown header type 7f
Kernel driver in use: Altera DMA


From other posts I've seen, I would think that this should actually output something more like this:

sudo lspci -vvv -s 02:00.0
02:00.0 Non-VGA unclassified device: Altera Corporation Device e003 (rev 01)
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 40
... and so on


Can someone help me figure out what's going wrong here and how I can fix it?


Thank you for your time,

Best regards, Alex
Attached Files
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Cyclone 10 GX Maximum LVDS Rate

May 31, 2018, 7:37 pm
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Hi,

what is maximum LVDS rate for Cyclone 10 GX devices?
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Prime Pro Edition : Source files - meaning of folder "tmp-clearbox"; Version Control

June 1, 2018, 1:00 am
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In Prime Standard Version, there was a folder "db" and a folder "incremental-db". If there occured problems with Quartus, it often helped to delete this folders and run compilation again. In Prime Pro these folders do not exist any more. There are some new folders now: Can the folder "tmp-clearbox" be deleted in case of problems without loss of sourcefiles or essential information?
Additional question:
If I use Version control software in Prime Pro, which files should be set under version control. So far I found out that ".IP" folders have to added compared to Prime Standard. Which other files (beside these already in Prime standard edition) have also to be set under Version control (like SVN or Git) ?
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Cyclone III EP3C10F256C6N JTAG TMS TDI internal pull-up power?

June 1, 2018, 1:39 am
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Hi

Cyclone III EP3C10F256C6N VCCIO Bank1 : 1.8V

After use PS_MODE to download rbf file.
The TMS and TDI two pin will have internal pull-up.
It's seems not pull up to VCCIO1,have some leakage path will cause VCCIO1 to 1.9V
If I short TMS and TDI to GND, can make VCCIO1 back to 1.8V.

Does any body the detail TMS and TDI internal pull-up circuit?
Is possible turn off the internal pull-up after download rbf file?


Thanks a lot for help
Albert
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Why do Altera University Program SD card drivers not have file delete function?

June 1, 2018, 2:09 am
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The Altera University Program SD card drivers have functions to open and close file and also to search through the root directory. There is no function to delete a file. Since the basic FAT16 functionality was already implemented to make it possible to read and write FAT16 SD cards, why has the file delete function been left out?
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PLL Warnings appearing with Quartus Prime

June 1, 2018, 4:35 am
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Hi,
I have three PLLs in my Cyclone V design.
Since I moved from Quartus II v15.0.2 to Quartus Prime v17.1.1 I get these outlandish warnings appearing (see attached image).
Does any one know what it's all about ?
The design is working fine but these warnings are a bit upsetting...
Many thanks in advance,

Manu
Attached Images
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Migration from C6 to C8

June 1, 2018, 6:51 am
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Hallo

We have a DE0-NANO Board with EP4CE22F17C6 FPGA. Is it possible to download a file which is compiled for EP4CE22F17C8 and get it running on the DE0 NANO board, keeping the pin-out and all the other settings the same? As they are from the same EP4CE22 group and Altrea suggest that there is a vertical migration is possible.

Can anyone please let me know if its possible and if possible how it can be done?
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