// Interface definition
interface EMIF_Bus;
input logic [1:0] EMIF_addr;
output logic [15:0] EMIF_data;
input logic EMIF_readEnable;
endinterface
// Top level
module interface_top (
input clk,
input reset,
EMIF_Bus chip_io
);
// Instantiating lower module
interface_sv SYSTEMVERILOG_DUT
(
.clk (clk),
.reset (reset),
.module_io (chip_io)
);| equ bit_24_pattern, 0x01000000 |
|||
| /* This program provides a simple example of code for the ARM A9. It: |
|||
| * 1. starts the ARM A9 private timer |
|||
| * 2. loops forever, toggling the HPS green light LEDG when the timer expires |
|||
| */ |
|||
| .text |
|||
| .global _start |
|||
| _start: |
|||
| LDR R0, =0xFF709000 // GPIO1 base address |
|||
| LDR R1, =0xFFFEC600 // MPCore private timer base address |
|||
| LDR R2, =bit_24_pattern // value to turn on the HPS green light LEDG |
|||
| STR R2, [R0, #0x4] // write to the data direction register to set |
|||
| // bit 24 (LEDG) of GPIO1 to be an output |
|||
| LDR R3, =200000000 // timeout = 1/(200 MHz) x 200×10∧6 = 1 sec |
|||
| STR R3, [R1] // write to timer load register |
|||
| MOV R3, #0b011 // set bits: mode = 1 (auto), enable = 1 |
|||
| STR R3, [R1, #0x8] // write to timer control register |
|||
| LOOP: |
|||
| STR R2, [R0] // turn on/off LEDG |
|||
| WAIT: LDR R3, [R1, #0xC] // read timer status |
|||
| CMP R3, #0 |
|||
| BEQ WAIT // wait for timer to expire |
|||
| STR R3, [R1, #0xC] // reset timer flag bit |
|||
| EOR R2, R2, #bit_24_pattern // toggle LEDG value |
|||
| B LOOP |
|||
| .end |
|||
| equ bit_24_pattern, 0x01000000 |
|||
| /* This program provides a simple example of code for the ARM A9. It: |
|||
| * 1. starts the ARM A9 private timer |
|||
| * 2. loops forever, toggling the HPS green light LEDG when the timer expires |
|||
| */ |
|||
| .text |
|||
| .global _start |
|||
| _start: |
|||
| LDR R0, =0xFF709000 // GPIO1 base address |
|||
| LDR R1, =0xFFFEC600 // MPCore private timer base address |
|||
| LDR R2, =bit_24_pattern // value to turn on the HPS green light LEDG |
|||
| STR R2, [R0, #0x4] // write to the data direction register to set |
|||
| // bit 24 (LEDG) of GPIO1 to be an output |
|||
| LDR R3, =200000000 // timeout = 1/(200 MHz) x 200×10∧6 = 1 sec |
|||
| STR R3, [R1] // write to timer load register |
|||
| MOV R3, #0b011 // set bits: mode = 1 (auto), enable = 1 |
|||
| STR R3, [R1, #0x8] // write to timer control register |
|||
| LOOP: |
|||
| STR R2, [R0] // turn on/off LEDG |
|||
| WAIT: LDR R3, [R1, #0xC] // read timer status |
|||
| CMP R3, #0 |
|||
| BEQ WAIT // wait for timer to expire |
|||
| STR R3, [R1, #0xC] // reset timer flag bit |
|||
| EOR R2, R2, #bit_24_pattern // toggle LEDG value |
|||
| B LOOP |
|||
| .end |
|||
$ source /home/drd/intelFPGA_pro/18.0/hld/init_opencl.sh
INTELFPGAOCLSDKROOT is set to /home/drd/intelFPGA_pro/18.0/hld. Using that.
Will use $QUARTUS_ROOTDIR_OVERRIDE= /home/drd/intelFPGA_pro/18.0/quartus to find Quartus
AOCL_BOARD_PACKAGE_ROOT is set to /home/drd/intelFPGA_pro/18.0/hld/board/a10_ref. Using that.
Adding /home/drd/intelFPGA_pro/18.0/hld/bin to PATH
Adding /home/drd/intelFPGA_pro/18.0/hld/host/linux64/lib to LD_LIBRARY_PATH
Adding /home/drd/intelFPGA_pro/18.0/hld/board/a10_ref/linux64/lib to LD_LIBRARY_PATH
$ aocl flash acl0 boardtest.aocx
Cannot find board_env.xml in /home/drd/intelFPGA_pro/18.0/hld/board/s10_refSlack______From Node ____________________________________ ____to Node __________Launch Clock ____________________________________________________________________________Latch clock____Relationship __Clock Skew ___Data Delay
-9.115 ____ io_control:io_control_inst1|data_out[21] _______ dq[21] _______ pll_inst_100|pll_100_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ______ clk_100____ 10.000 ____ -10.144______2.901flopping_data_out_proc : process(CLK, RESET)begin
if (RESET = '0') then
data_out <= (others => '0');
elsif (rising_edge(CLK)) then
data_out <= Fin_DATA_ram; -- comes from inside FPGA Design
end if;
end process flopping_data_out_proc;
mux_data_out_proc : process(slrd_en, data_out)
begin
if (slrd_en = '0') then
DATA <= data_out; -- DATA is output of IO Control and wired to DQ
else
DATA <= (others => 'Z');
end if;
end process;Warning (332049): Ignored create_clock at SDC1.sdc(2): Incorrect assignment for clock. Source node: CLOCK_50_B5B already has a clock(s) assigned to it. Use the -add option to assign multiple clocks to this node. Clock was not created or updated.
Info (332050): create_clock -name CLK1 -period 20.0 [get_ports {CLOCK_50_B5B}]