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DSP Builder with QuestaSim

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Dear Community

Currently we're using DSP builder in combination with ModelSim (SE or PE). Since we want to use QuestaSim from now on, I'm wondering if there is any possibility to use DSP builder with QuestaSim instead of ModelSim. The reason is that we don't want to have both installations to be installed on our computers.

Any help is highly appreciated.

Best,

Stefan

Looking for Bemicro CV A9

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Hello,

Greetings to you all from a new member and I kindly ask you to forgive me if this post breaks any forum rules.

Does anybody have a (now sadly discontinued) Bemicro CV A9 board to sell? It has a large Cyclone V FPGA with 301k LE which I would love to get my hands on :)

Regards,

TSE IEEE1588 feature

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Hello!
I want to receive a timestamp for an incoming message. The documentation (Intel FPGA Triple-Speed Ethernet IP Core User Guide) says "In the receive datapath, the IEEE 1588v2 feature provides a timestamp for all receive
frames. The timestamp is aligned with the avalon_st_rx_startofpacket signal." What does it mean? Can I get the timestamp from avalon bus?

Quartus help - RTL Viewer does't update after changes in the code

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Hello,

On the very first time i open the RTL Viewer in any new project - it generates a schematic.
But if i change something in the Verilog code, compile, and open the RTL Viewer again, the RTL Viewer doesn't update accordingly.

The only way i can get it to update is clicking:
project > clean project
and then open the RTL Viewer again.

is there a nicer, more direct way to do it?

thx

DE1-SOC ethernet project. (please HELP!)

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Hi guys

I am trying to build this project for a long time. Now, I reach a point where i really need help from a community like this one, so please don't leave me a lone with this issue :(

Objective of this project:
I have DE1-SoC board from terasic and i would like to send data from FPGA to PC through 1G ethernet port. The data is high sampling rate so i need to use the ethernet efficiently.

What i did until now:
I've used the DE1-SoC-GHRD demonstration example as a start point. I know how to control LEDs and read switched position through hps. I know that the ethernet is connected directly to the HPS. However, I don't know how to read and write in the ethernet port!!!

Please help me guys

Design Space Explorer does not make use of all CPUs in the system

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I have Quartus Prime 18.0 Standard, and I've been using it on a Windows-based dual Xeon E5-2699 system (it's high end as CPUs go, but not particularly cutting-edge - these CPUs are almost 4 years old.) Each CPU has 22 cores with 2 hyperthreaded logical processors each.

Since compilation is incredibly slow (I am currently working on a design that averages 2 hours per compile, most of it spent in the fitter), proper use of available resources is a must.

First of all, each instance is capped by the options at 16 processors. That I can understand (maybe the algorithm does not parallelize well), but there's still room for improvement.

Since timing seems to vary quite a bit between runs, I took to using Design Space Explorer to do multiple compiles in parallel. As a side note, it would be nice if DSE let me vary the code between exploration points (e.g. define a different macro in each point, so I could leverage that macro to try different permutations of my code.) But I digress.

Now, the problem is that all instances launched by DSE are locked to socket #1. So, I have 8 instances trying to compile at once, but they are all crowding the same 22 cores, so, whenever they all go multithreaded, they start competing for resources. I see 100% CPU usage in socket #1 and 0% socket usage in socket #2. As a result, compilation takes longer than it should.

From the point of view of Windows API, CPUs are arranged in two "processor groups". The simplest solution would be to detect the number of processor groups and to pick one of the groups at random when Quartus is launched. It's literally 10 lines of code.

What's especially baffling is that I am somehow prevented from messing with process affinity directly. I'd be willing to move some instances onto socket #2 by hand through the task manager, except, if I try to do that to any of the 8 instances of quartus_fit.exe, I get an error message, "Unable to access or set process affinity" / "The operation could not be completed" / "Access is denied". I never realized it was even possible to block access to process affinity. (This is Windows Server 2012 and I'm doing it as Administrator, so, no UAC issues.) I can reassign affinities of quartus_sh.exe and quartus_worker.exe (not that it does me any good). And the quartus_fit.exe process is not protected, because I can attach to it with a debugger just fine. It just won't let me touch its affinity for some reason.

How do I go about submitting a bug report / feature request?

preloader-mkpimage binary from SOC EDS V17.0 is not working

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I have installed SOC EDS Standard V17.0 on Ubuntu 17.10. Ubuntu is installed in Virtual Box.
I am able to create "preloader-mkpimage.bin" and "uboot.img" by using our customized handsoff file. But "preloader-mkpimage.bin" is not working on our board.

"preloader-mkpimage.bin" and "uboot.img" created on SOC EDS Standard V14.0 with the same handsoff file is working correctly on our board.

Is there any specific configuration needs to be done for upgrading SOC EDS Standard V17.0 from SOC EDS V14.0 OR is there any specific more input needs to be given in V17.0

SystemVerilog logic type as bidir

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Hello,

I'm new to SystemVerilog and have a question about a warning Quartus is throwing. I'm working with a design done by someone else.
In my code I have a 2 interfaces which have port type logic. In the module there is assignment of one logic type to another... for example

interface typeA();
logic[3:0][3:0] mem_A;
endinterface


interface typeB();
logic[3:0] b1;
logic[3:0] b2;
logic[3:0] b3;
endinterface

module dut(typeA in, typeB out);
assign out.b1[0] = in.mem_A[0];
assign out.b2[1] = in.mem_A[1];
assign out.b3[2] = in.mem_A[2];
endmodule

I'm trying to get rid of this warning but don't know what do to since the interfaces are being used multiple times all over the design.
Warning (10665): Bidirectional port "IN.pix[0][2]" at If.sv(47) has a one-way connection to bidirectional port "OUT.grn[0][2]"


Thanks in advance.

Which IO standard needs to be used? 200 MHz 1.8 V

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Hi,

I need to drive an input at a board which is connected to my board through samtec connectors at 200 Mhz, 1.8V, single ended. In cyclone 10 GX device, Which IO standard should I pick?

LVDS Signal DC offset and AC Swing

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Hi, What is the value of LVDS DC offset and LVDS AC Swing of Cyclone 10 GX devices?

RTL Viewer does't update after changes in the code and compilation

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Quote:

Hello,

On the very first time i open the RTL Viewer in any new project - it generates a schematic.
But if i change something in the Verilog code, compile, and open the RTL Viewer again, the RTL Viewer doesn't update accordingly.

The only way i can get it to update is clicking:
project > clean project
and then open the RTL Viewer again.

is there a nicer, more direct way to do it?

thx
I asked the original question HERE but now noticed it is more suitable for this forum.
In the original post i have screenshots.

would appriciate for help

How to read the Qsys ADC component data register in C directly

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I have a Qsys design with NIOS2 C program. The program will read the Altera ADC component of the Qsys system (Max10 on-chip ADC) as each data point becomes ready. The simplest scenario. No 'sample train' or sequencer required. Just check for new ADC value and read the value in the data register. I have the ADC configured in Qsys for dedicated input on ANIN, channel 0.

Based on my understanding of a similar enquiry here in another thread,
http://www.alteraforum.com/forum/showthread.php?t=57979
I am wondering if ADC read is as simple as 'knowing the ADC data register address to read from, and reading it using a pointer'.

The pages I am reading look to suggest that, to read a Qsys IP register address, we can simply do the following:

For example, let's say my ADC value register in Qsys is at mem location 0x5000.

step 1: initialize a pointer to the data address of ADC register as - " int *adc_data = 0x5000; "
step 2: Read data using - " ADC_value = adc_data[0]; "

When I 'build' this is get a caution that "initialization makes pointer from integer without a cast [-Wint-conversion]". I'm not sure how to interpret the message, or my mistake, but it looks like I don't have it right yet.

I'm hoping someone can help me understand, or provide a simple example.

Thanks,

NIOSII SBT (eclipse Mars) corresponded with quartus 17.1 pro crushes often

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Hello,
I am using NIOS2 SBT (based on eclipse Mars) which is part of quartus 17.1.2.304 Pro and it crushes quite often (at last once every hour) - it happens on more than 1 pc (at least 3 different PCs and laptops).
more than that, one time after a crash - the eclipse didnt start up and i received an error in sbt log file about workspace error, i was tryng to remove workspace folder, restart the computer with no positive results so i uninstalled the quartus and installed again.

my OS is win7 64bit

it makes developing not easy and i would like to know if there's a solution for the SBT crashes issue.

thanks,
Ran

Fatal error on quartus ||

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Hello everybody,
today i was testing my code and when i compile it the program gives me this error:

*** Fatal Error: Access Violation at 0X00007FFDF4F788BB
Module: quartus_map.exe
Stack Trace:
0xa88ba: VRFX_ELABORATOR::elaborate + 0x4f1aa
0xab0e5: VRFX_ELABORATOR::elaborate + 0x519d5
0x190222: VRFX_ELABORATOR::operator= + 0x80932
0x1908bc: VRFX_ELABORATOR::operator= + 0x80fcc
0x60316: VRFX_ELABORATOR::elaborate + 0x6c06
0x598fc: VRFX_ELABORATOR::elaborate + 0x1ec
0xd6f93: sgn_clear_check_ip_functor + 0x3a323
0xdac3f: sgn_clear_check_ip_functor + 0x3dfcf
0xdc525: sgn_clear_check_ip_functor + 0x3f8b5
0xa57d4: sgn_clear_check_ip_functor + 0x8b64
0xb5efc: sgn_clear_check_ip_functor + 0x1928c
0xb286a: sgn_clear_check_ip_functor + 0x15bfa
0xb5f4c: sgn_clear_check_ip_functor + 0x192dc
0xba0dd: sgn_clear_check_ip_functor + 0x1d46d
0x10de2: sgn_qic_full + 0x152






0x128ed: qexe_get_command_line + 0x206d
0x1573e: qexe_process_cmdline_arguments + 0x59e
0x15851: qexe_standard_main + 0xa1


0xa7f8: msg_exe_fini + 0x58
0xaf3c: msg_exe_fini + 0x79c
0x1f14: MEM_SEGMENT_INTERNAL::~MEM_SEGMENT_INTERNAL + 0x194
0xb8bf: msg_exe_main + 0x8f


0x13033: BaseThreadInitThunk + 0x13
0x71550: RtlUserThreadStart + 0x20


End-trace


Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition

can someone help me understand what this is? and also how to solve this problem? thank you for your answer. :(:(

Nios DDR3 Test Example Project TimeQuest Negative Setup Slack

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Hello everyone,

I've been trying to understand the workings of the timing analyser recently. I need to implement an SDRAM Controller with Uniphy in my design.
So I opened up an example project called "SoCKit_DDR3_Nios_Test. I noticed it is very similar to mine, it has a nios processor, onchip mem, clock, and so on.

After compiling and constraining the I received a setup violation error. I don't know what is wrong with my constraint. I doubt I need to use set_input_delay or set_output_delay, since the sdc file doesn't even have clock groupings, which I added later on to try to repair the setup slack. The clock groupings managed to correct the negative slack on the generated clock "u0|pll_qsys|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk"
This is my sdc file.

Code:


create_clock -period 20 [get_ports OSC_50_B3B]
create_clock -period 20 [get_ports OSC_50_B4A]
create_clock -period 20 [get_ports OSC_50_B5B]
create_clock -period 20 [get_ports OSC_50_B8A]
derive_pll_clocks
derive_clock_uncertainty
set_clock_groups -asynchronous -group {OSC_50_B3B \
                                                    OSC_50_B4A \
                                                    OSC_50_B5B \
                                                    OSC_50_B8A \
                                        } \
                                        -group {
                                                    u0|pll_qsys|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] \
                                                    u0|pll_qsys|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \
                                        } \
                                        -group { \
                                                    u0|mem_if_ddr3_emif_fpga|DDR3_Qsys_mem_if_ddr3_emif_fpga_p0_sampling_clock \
                                        } \
                                        -group { \
                                                    u0|mem_if_ddr3_emif_fpga|pll0|pll_addr_cmd_clk \
                                                    u0|mem_if_ddr3_emif_fpga|pll0|pll_avl_clk \
                                                    u0|mem_if_ddr3_emif_fpga|pll0|pll_dq_write_clk \
                                                    u0|mem_if_ddr3_emif_fpga|pll0|pll_write_clk \
                                        } \
                                        -group { \
                                                        u0|mem_if_ddr3_emif_fpga|pll0|pll_afi_clk \
                                        } \
                                        -group { \
                                                    DDR3_CK_n \
                                                    DDR3_CK_p \
                                                    DDR3_DQS_n[0]_OUT \
                                                    DDR3_DQS_n[1]_OUT \
                                                    DDR3_DQS_n[2]_OUT \
                                                    DDR3_DQS_n[3]_OUT \
                                                    DDR3_DQS_p[0]_IN \
                                                    DDR3_DQS_p[0]_OUT \
                                                    DDR3_DQS_p[1]_IN \
                                                    DDR3_DQS_p[1]_OUT \
                                                    DDR3_DQS_p[2]_IN \
                                                    DDR3_DQS_p[2]_OUT \
                                                    DDR3_DQS_p[3]_IN \
                                                    DDR3_DQS_p[3]_OUT \
                                        } \

I can't really wrap my head around the behind-the-scene workings of Altera. Can someone please explain me?
I look forward to any replies :)

Edit: BTW I'm using Quartus 14.1
Attached Images

get clock feeding pin

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Hi all,

I need to retrieve the clock feeding a specific pin in quartus. It seems there is no available command that can do that.
I found this description on Intel web site that illustrates how to do by writing a whole procedure.

https://www.altera.com/support/suppo...procedure_code

I've tested this procedure but it seems not working.
Has anyone encountered something like this?
Is there another way to do that?

Ep3c25f256c8n vs. Ep3c25f256c8nad

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Hello,
I was looking at ordering some of the EP3C25F256C8N parts and was told that a part ending in AD is available.

Does anyone know what the difference is if any between the EP3C25F256C8N parts and part ending in "AD" EP3C25F256C8NAD?

I was told the AD stands for Agency Order but have no clue what that means.

Picture of the part ending in AD is attached.

Thanks
Attached Images

Monte Carlo Black-Scholes Asian Options Pricing Design Example

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After several false starts, I have a working OpenCL environment with immense help from Nallatech. Since the type of problems I want to solve is similar to Intel's Monte Carlo BS pricing example, I wanted to try this example out on a 395AB Nallatech board which has a Stratix V GXAB processor, 32GB of memory. When compiling the example, it is failing that it can't fit. Anyone have any idea? Its a simple example, so I am surprised that it failed on this board?

https://www.altera.com/support/suppo...k-scholes.html

Thanks,

QG

FPGA MAX 10: JTAG secure mode

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Hi,

I would like to Enable JTAG secure mode in MAX 10 device. While generating encrypted .pof file; it doesn't show any option to enable/diable JTAG security mode. What would be a best way to do that?

Thank you,
Regards,
Jay

Qsys creating the wrong number of bits for some native_phy_tx buses

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In Qsys, I have specified a straightforward TX/RX duplex transceiver with 4 channels.
After Generate in Qsys, the block symbol shows that the serial and data I/O busses contain exactly the correct numbers of bits.
However, several other I/Os have width 8, instead of 4: rx_datak, rx_disperr, rx_errdetect, rx_patterndetect, rx_runningdisp, rx_syncstatus, and tx_datak

There was an earlier version of the design that instantiated the transceiver with 8 channels, but the design has been revised thoroughly.
Could there be a lingering "design state" variable that I'm unaware of?

What else might be going on?

Hopeful thanks in advance for suggestions or insight.
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