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Trying to run QNX RTOS on DE10-Standard Kit with CycloneV SoC

June 7, 2018, 3:01 pm
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Hello,
I have a DE10-Standard Kit with Cyclone V SoC. My aim is to run QNX on the HPS via SD Card. The Flash/Boot Image will have a pre-loader and U-Boot followed by QNX image and then the application.

Now I am going through many documentation of how one can customise the BSP provided by QNX. But I want to confirm whether it is possible to boot any other RTOS other than Linux, as given by Terasic. The kit has certain configuration switches (MSEL SEttings) to toggle between Default mode and Linux Booting via SD Card. Can any please clarify if there is any dependency of HW which can affect preloader and U-Boot taken from QNX and running QNX on it?

I also wish to know where can I find a start up code which points to the SD Card after initialising the Clock, Watch and other system parameters? This way, my SD Card having the Preloader, U-Boot and the RTOS image can run from the SD Card.

Kindly please help me out here. Really struggling for almost a week.

Thanks and Regards,
Guruprakash Singh
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Arria 10 spine clock region overused

June 7, 2018, 3:07 pm
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Hi,

I'm trying to build a fimware with several transceiver banks. If I use 4 banks, it's fine. But 5 banks cause congestion in the "spine clock region" and the compilation sits in "IO Placement" for about an hour and eventually gives up with the follow error (my guess at the relevant part is highlighted in red). I've not see this error before. Any thoughts would be appreciated.


Error (14996): The Fitter failed to find a legal placement for all periphery components
Info (14987): The following components had the most difficulty being legally placed:
Info (175029): Clock core fanout containing node LLI:lli_inst|GWT_6ch:\multiLink_gen_loop:1:multiLi nk_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank _0|gwt_tx_top:gwt_tx_4|tx_fifo:tx_fifo_inst|dcfifo _mixed_widths:dcfifo_mixed_widths_component|dcfifo _k1t1:auto_generated|altsyncram_5k91:fifo_ram|ram_ block9a0 and 31 other node(s) driven by auto-promoted clock driver
...
Info (175029): Clock core fanout containing node LLI:lli_inst|GWT_6ch:\multiLink_gen_loop:3:multiLi nk_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank _0|gwt_rx_top:gwt_rx_5|pile_and_shift:PILE|data_sc rambler_input[106] and 948 other node(s) driven by auto-promoted clock driver LLI:lli_inst|GWT_6ch:\multiLink_gen_loop:3:multiLi nk_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank _0|GWT_6ch_altera_xcvr_native_a10_161_pn5wopi:xcvr _native_a10_0|twentynm_xcvr_native:g_xcvr_native_i nsts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_re v_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev _20nm5:inst_twentynm_pcs|w_hssi_rx_pld_pcs_interfa ce_pld_pcs_rx_clk_out~CLKENA0 and auto-promoted clock driver LLI:lli_inst|GWT_6ch:\multiLink_gen_loop:3:multiLi nk_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank _0|altera_reset_controller:rst_controller|altera_r eset_synchronizer:alt_rst_sync_uq1|altera_reset_sy nchronizer_int_chain_out~CLKENA0 (9%)
Info (175029): auto-promoted clock driver LLI:lli_inst|GWT_6ch:\multiLink_gen_loop:4:multiLi nk_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank _0|GWT_6ch_altera_xcvr_native_a10_161_pn5wopi:xcvr _native_a10_0|twentynm_xcvr_native:g_xcvr_native_i nsts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_re v_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev _20nm5:inst_twentynm_pcs|w_hssi_rx_pld_pcs_interfa ce_pld_pcs_rx_clk_out~CLKENA0 (6%)
Info (175029): auto-promoted clock driver LLI:lli_inst|GWT_6ch:\multiLink_gen_loop:4:multiLi nk_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank _0|GWT_6ch_altera_xcvr_native_a10_161_pn5wopi:xcvr _native_a10_0|twentynm_xcvr_native:g_xcvr_native_i nsts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_re v_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev _20nm5:inst_twentynm_pcs|w_hssi_tx_pld_pcs_interfa ce_pld_pcs_tx_clk_out~CLKENA0 (5%)
Error (14986): After placing as many components as possible, the following errors remain:
Error (13081): The Fitter cannot route to 1 clock core fanout
Info (14596): Information about the failing component(s):
Info (13207): The clock core fanout consists of 40 node(s)
Info (13205): Sample node name: LLI:lli_inst|GWT_6ch:\multiLink_gen_loop:4:multiLi nk_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank _0|gwt_tx_top:gwt_tx_0|coe_GWT_TX[0]
Info (13208): This core logic is driven by 1 clock source(s)
Info (14900): auto-promoted clock driver LLI:lli_inst|GWT_6ch:\multiLink_gen_loop:4:multiLi nk_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank _0|GWT_6ch_altera_xcvr_native_a10_161_pn5wopi:xcvr _native_a10_0|twentynm_xcvr_native:g_xcvr_native_i nsts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_re v_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev _20nm5:inst_twentynm_pcs|w_hssi_tx_pld_pcs_interfa ce_pld_pcs_tx_clk_out~CLKENA0
Info (14894): This signal is currently using global clock 13, with the buffer placed at CLKCTRL_1C_G_I13
Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (224, 213) due to related logic
Info (175015): The I/O pad rx_gbt[24] is constrained to the location PIN_R3 due to: User Location Constraints (PIN_R3)
Info (14709): The constrained I/O pad is contained within a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_TX_PLD_PCS_INTERFACE, which drives this auto-promoted clock driver
Info (175015): The I/O pad rx_gbt[25] is constrained to the location PIN_P5 due to: User Location Constraints (PIN_P5)
Info (14709): The constrained I/O pad is contained within a HSSI_RX_CHANNEL_CLUSTER, which is contained within a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_10G_TX_PCS, which drives a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_TX_PLD_PCS_INTERFACE, which drives this auto-promoted clock driver
Info (175015): The I/O pad rx_gbt[26] is constrained to the location PIN_N3 due to: User Location Constraints (PIN_N3)
Info (14709): The constrained I/O pad is contained within a HSSI_RX_CHANNEL_CLUSTER, which is contained within a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_8G_RX_PCS, which drives a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_10G_TX_PCS, which drives a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_TX_PLD_PCS_INTERFACE, which drives this auto-promoted clock driver
Info (175015): The I/O pad rx_gbt[27] is constrained to the location PIN_M5 due to: User Location Constraints (PIN_M5)
Info (14709): The constrained I/O pad is contained within a HSSI_RX_CHANNEL_CLUSTER, which is contained within a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_8G_RX_PCS, which drives a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_8G_RX_PCS, which drives a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_10G_TX_PCS, which drives a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_TX_PLD_PCS_INTERFACE, which drives this auto-promoted clock driver
...
Error (16234): No legal location could be found out of 30 considered location(s). Reasons why each location could not be used are summarized below:
Error (177032): Section clock (SCLK) network in spine clock region bounded by (111,87) and (159,113) is overused
Info (18630): This congestion may be avoided by moving or disabling promotion of any of the following competing signals:
Info (175030): Unroutable signal:
Info (175026): Source: auto-promoted clock driver LLI:lli_inst|GWT_6ch:\multiLink_gen_loop:4:multiLi nk_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank _0|GWT_6ch_altera_xcvr_native_a10_161_pn5wopi:xcvr _native_a10_0|twentynm_xcvr_native:g_xcvr_native_i nsts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_re v_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev _20nm5:inst_twentynm_pcs|w_hssi_tx_pld_pcs_interfa ce_pld_pcs_tx_clk_out~CLKENA0
Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (224, 213) due to related logic
Info (175015): The I/O pad rx_gbt[24] is constrained to the location PIN_R3 due to: User Location Constraints (PIN_R3)
Info (14709): The constrained I/O pad is contained within a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_TX_PLD_PCS_INTERFACE, which drives this auto-promoted clock driver
...
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Problem in interacing TI ADC eval module (ADC12DJ3200EVM) with Arria 10 SoC.

June 7, 2018, 5:25 pm
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Hi,

I am trying to interface the Texas Instruments ADC eval board to Arria 10 SoC using FMC+ to FMC interface. The interface uses JESD204B IP to receive the sampled data from ADC to the Transceiver PHY. I am using Altera 10 design example from TI to test the interfacing (); I follow the steps mentioned in the user guide (attached) to compile the design example, program the eval board, and analyze the data received using Signal Tap Logic Analyzer. I am providing a 250MHz sinusoidal signal at Channel A at the ADC. I am expected to see some data, but I see nothing. The only change I have made is assigning the device name to 10AS066NF340E2SG from 10AX115S2F45I1SGE2 and the corresponding pins in pin planner, which compiled with no error. I am wondering if you could help me in figuring out the problem. I find that the dev_sync_n signal is low; but I am not sure why. PFA.

Thanks
Attached Images
Attached Files
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Question about REFCLK_GXB_CHB and REFCLK_GXB_CHT in Tranceivers of Arria10 SX

June 7, 2018, 7:11 pm
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Hi, what's the difference between REFCLK_GXB_CHB and REFCLK_GXB_CHT in Tranceivers of Arria10 SX？
Does the "CHB" refer to Bottom and "CHT" refer to Top?
I plan to design a SRIO 4x in a tranceiver bank，should I connect both CHB and CHT to a clock source individually，or just connect one of them to a clock source while connect the other one to GND？
Thanks.
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FPGA programming: Block Design files or Verilog line by line programming?

June 7, 2018, 10:38 pm
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Just starting to learn Quartus for FPGA programming. I'm coming from a CPLD programming background.

I'm impressed with the Block Design files programming approach. This YouTube demo is excellent:

https://www.youtube.com/watch?v=jxkNilK__yE

While my applications will be simple probably not much more than a few CPLDs I worried if there will be limitations in what I can do later on.
Also looking at the final Verilog type source type code it seems very complex and I worried that I will fill up the FPGA inefficiently.

What are the pros and cons of both approaches.

John
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Quartus_cdb (17.1/18.0) crashes while generating VQM for StratixV for a simple adder

June 7, 2018, 11:34 pm
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Hi All,

I am using Quartus17.1 as well as Quartus 18.0

quartus_cdb crashes with following error only when StratixV family is used:
*** Fatal Error: Segment Violation at (nil)
Module: quartus_cdb
Stack Trace:
0xbbd90: DEV_DEVICE::get_pad_info() const (ddb_dev)

End-trace

The verilog file, Add_24Ux24U_24U_4.v :
###########################
module Add_24Ux24U_24U_4 (
in2,
in1,
out1
);
input [23:0] in2,
in1;
output [23:0] out1;
wire [23:0] asc001;

assign asc001 =
+(in2)
+(in1);

assign out1 = asc001;
endmodule
#########################

The tcl file (syn.tcl):
#########################
load_package flow
load_package report
load_package sdc

set module "Add_24Ux24U_24U_4"

proc syn { module family verilogInput} {
set proj [project_new -overwrite $module]
set_global_assignment -name FAMILY $family
set_global_assignment -name DEVICE Auto
set_global_assignment -name VERILOG_FILE ${module}.v
set_global_assignment -name NUM_PARALLEL_PROCESSORS 2
set_instance_assignment -name VIRTUAL_PIN ON -to in*
set_instance_assignment -name VIRTUAL_PIN ON -to in*
set_instance_assignment -name VIRTUAL_PIN ON -to out*
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

execute_module -tool map
execute_module -tool fit
execute_module -tool cdb -args "--vqm=${module}.vqm"
project_close
}

syn $module "StratixV" $module
#########################

Command used to run
> quartus_sta -t syn.tcl

Please let me know any solution to this issue.

Thanks,
Srinivasa
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Nios DDR3 Test Example Project TimeQuest Negative Setup Slack

June 7, 2018, 11:45 pm
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Hello everyone,

I've been trying to understand the workings of the timing analyser recently. I need to implement an SDRAM Controller with Uniphy in my design.
So I opened up an example project called "SoCKit_DDR3_Nios_Test. I noticed it is very similar to mine, it has a nios processor, onchip mem, clock, and so on.

After compiling and constraining the I received a setup violation error. I don't know what is wrong with my constraint. I doubt I need to use set_input_delay or set_output_delay, since the sdc file doesn't even have clock groupings, which I added later on to try to repair the setup slack. The clock groupings managed to correct the negative slack on the generated clock "u0|pll_qsys|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk"
This is my sdc file.

Code:

create_clock -period 20 [get_ports OSC_50_B3B]
create_clock -period 20 [get_ports OSC_50_B4A]
create_clock -period 20 [get_ports OSC_50_B5B]
create_clock -period 20 [get_ports OSC_50_B8A]
derive_pll_clocks
derive_clock_uncertainty
set_clock_groups -asynchronous -group {OSC_50_B3B \
                                                    OSC_50_B4A \
                                                    OSC_50_B5B \
                                                    OSC_50_B8A \
                                        } \
                                        -group {
                                                    u0|pll_qsys|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] \
                                                    u0|pll_qsys|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \
                                        } \
                                        -group { \
                                                    u0|mem_if_ddr3_emif_fpga|DDR3_Qsys_mem_if_ddr3_emif_fpga_p0_sampling_clock \
                                        } \
                                        -group { \
                                                    u0|mem_if_ddr3_emif_fpga|pll0|pll_addr_cmd_clk \
                                                    u0|mem_if_ddr3_emif_fpga|pll0|pll_avl_clk \
                                                    u0|mem_if_ddr3_emif_fpga|pll0|pll_dq_write_clk \
                                                    u0|mem_if_ddr3_emif_fpga|pll0|pll_write_clk \
                                        } \
                                        -group { \
                                                        u0|mem_if_ddr3_emif_fpga|pll0|pll_afi_clk \
                                        } \
                                        -group { \
                                                    DDR3_CK_n \
                                                    DDR3_CK_p \
                                                    DDR3_DQS_n[0]_OUT \
                                                    DDR3_DQS_n[1]_OUT \
                                                    DDR3_DQS_n[2]_OUT \
                                                    DDR3_DQS_n[3]_OUT \
                                                    DDR3_DQS_p[0]_IN \
                                                    DDR3_DQS_p[0]_OUT \
                                                    DDR3_DQS_p[1]_IN \
                                                    DDR3_DQS_p[1]_OUT \
                                                    DDR3_DQS_p[2]_IN \
                                                    DDR3_DQS_p[2]_OUT \
                                                    DDR3_DQS_p[3]_IN \
                                                    DDR3_DQS_p[3]_OUT \
                                        } \
I can't really wrap my head around the behind-the-scene workings of Altera. Can someone please explain me?
I look forward to any replies :)

BTW I'm using Quartus 14.1
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Configuration and initialization of HPS - I/O in Cyclone V

June 8, 2018, 1:16 am
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Hello,
I’m working on a bare-metal application with Altera Cyclone V with assembly language.
I need to configure the I/O bank properties before use the pin by the peripherals in HPS.
I read that this configuration is made in the Scan Manager by configuring the Scan Chains.
For that I have to write configuration words in the FIFO registers.
I cannot find data describing the words to write in the FIFO according to the I/O configuration.
Where can I find these information?
Where can I find these examples?
Thanks for your help
Jerome
Hello,
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Output FFT - all zeros

June 8, 2018, 2:55 am
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Hi,

I generated FFT-core in Qyartus 11.0,
sended data by Ethernet UDP from Matlab (data I see by SignalTap Analyzer),
but outputs of FFT-core are those: (see picture)

Please suggest, who understand what happends.
Attached Images
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Timing failure on internal paths

June 8, 2018, 4:12 am
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Hi dear,

The design failing the time on internal paths and on the same clock domain. The timing report is attached as image . This design works fine without any constraints.

Can please someone explain what could be the reason and what is the solution to resolve it?

Kind regards
Mohsin
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Stratix 10 Transceiver Latency

June 8, 2018, 4:35 am
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Hello,

Where can I find the latency numbers for the Stratix 10 gigabit transceivers? I've looked through the data sheet and user guide with no luck.

Thanks,
Dave
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Alpha Blending Mixer with alpha values

June 8, 2018, 6:16 am
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Hello everyone.

I am using Alpha Blending Mixer in my Qsys Project on Quartus 15.0.

I got the need of using alpha blend option of the core. In the datasheet of VIP Suite I noticed the following "The IP core does not use alpha values for the background layer (a0); you must tie the alpha0 port off to 0 when you instantiate the IP core in the parameter editor."

What's the correct way to instantiate an Avalon Streaming Sink to a hard value of "0" ?

Thanks in advance
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EyeQ on Arria 10 GX (Dev. Kit DK-DEV-10AX115S-A)

June 8, 2018, 8:18 am
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Hi,
i have a question about EyeQ Tool: is it present in Arria 10 GX?
I created a project with Reset Controller, ATX PLL, Native RX and Native TX.
When i run the Transceiver Toolkit the TX and RX are connected, then i start the test and the BER is 0. So the equalization-sweep was successful.
Now i would like to plot a EyeDiagram, is possible on Arria 10 GX?

(in this site it would seem so: https://www.altera.com/products/fpga...nsceivers.html)

Thanks,
Marco
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Interfacing FPGA pins to an external bidirectional bus.

June 8, 2018, 3:09 pm
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OK I've decided to go with Block Design Files approach to programming a IV Cyclone in Quartus. Seems easier than Verilog from scratch to me. My application has lots of pins but is fairly simple.

There is one catch however, I’m interfacing a number of the FPGA pins to an external
bidirectional bus
. Straight in & out pins are obvious.

For bidirectional I assume I use a symbol
ALT_OUTBUF_TRI.
Under “Symbol Properties/ports it has 3 names i, o, and oe.

It’s unclear to me how I access/connect up to the oe port with wires. The oe does not appear in the schematic

I assume I somehow raise (or lower) oe before reading in from the FPGA actual pin to inactivate the gates output and do the opposite when writing to the FPGA pin only this time drive the signal through the gate.

Can somebody point me to a .bdf file with FPGA pins interfaced to an external bidirectional pin or provide a simple picture.
Thanks in advance for helping somebody just getting started.
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With Transceivers, High-Speed Source-Synchronous Differential I/O Interfaces - LVDS

June 8, 2018, 4:03 pm
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Is there any limitation in the Cyclone 1o GX transceiver to create LVDS signal defined as Vocm 1.25 V , 0.3V to 0.4V differential swing with 2.5 Gbps (1.25 Ghz clock) by using the external shared clock with minimum 5 transceivers for source synchronous implementation ( 1 clock 4 data late at 2.5 Gbps data rate with 1.25 GHz )?
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High-Speed Source-Synchronous Differential I/O Interfaces in Cyclone 10 GX Devices

June 8, 2018, 4:18 pm
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Background:
My end goal is to implement source synchronous differential IO interface with Cyclone 10 GX devices : 4 data lanes with 1 clock line at 2.5 Gbps with 1.25 GHz.
Cylone 10 GX devices has dedicated LVDS lines with HARD IP Serializer and Deserializer which allow LVDS at 1.434 Gbps. This is a limitation in my application. I am trying to use transceivers for 2.5 Gbps instead of LVDS IO resources.


Question:
I am looking for a document or a design example or a reference design for High-Speed Source-Synchronous Differential I/O Interfaces in Cylone 10 GX Devices.


Extra Information:
For other current GX devices, it is also fine.

I found the following document published at 2006. I am looking for a updated version of it.

https://www.altera.com/en_US/pdfs/li...x_sgx52013.pdf
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Problems with kernel >= 4.x

June 9, 2018, 12:56 am
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Hi,

I currently trying to replace my kernel with version 3.17 with a newer
one with version greater than 4.x.
I tried several versions but I am facing some problems and maybe anybody
else had the same issues and know a fix.

1. Problem
The bridges are renamed from hps2fpga to br0 and so on. I am using the
standard sockit device tree for the Terasic DE1SoC.
Is this common that the old names are gone? And are the bridges now
enabled and disabled automatically?

2. Problem
I cannot configure the fpga by writing the rbf file to the /dev/fpga0 device.
# cat /sys/class/fpga_manager/fpga0/state
power off
It looks like the FPGA is not powered?!

Big thx in advance
gandi
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↧

MAX 10 CFM0 not programed

June 9, 2018, 1:51 am
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Hi there,
I conceived and validated a project on Max10 dev kit.
Now that the project is OK, we are in the process of developing a dedicated board, using 10M50SCE144 device which appeared good enough for that project.
The board has just been manufactured, and using JTAG header with a USB blaster, I'm able to program, run and debug the project.

However, when I power cycle the board, it does not start.
There is no time limited IPs or such things who could prevent me from running the devices detached.

After further investigations and many many different configurations tested, it appears that UFM is programed correctly into the flash, but not CFM0?
Illustration:
I programed .pof file into the device and it started correctly.
With Quartus programmer, I verified UFM: 100 % OK
I thus verified CFM0: it jumped to 54% (I guess skipping UFM) and then Failed!!! :(
I powered off/on the board: UFM is still there (meaning the flash is able to retain data!), but no track of CFM0 and the board did not start...

I may be foolishly missing something, but no way to figure out what...
Any advice?

Thanks
jylo
↧

Help with VHDL VGA

June 9, 2018, 3:37 am
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Hi everyone

I'm just trying to use vga through de2-115 board

https://eewiki.net/pages/viewpage.ac...ageId=15925278

I refer to this page and it works

but now I'm trying to make my own vga controller but it doesn't work

I think problem is on clock but it's just a guess

my monitor couldn't read signal from my code

I need your help

this is the top model

Code:
LIBRARY ieee;USE ieee.std_logic_1164.all;


entity VGA is
        port(
          CLK                :IN  std_LOGIC;
                RED                :OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
                GREEN                :OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
                BLUE                :OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
                h_sync        :OUT        STD_LOGIC;
                v_sync        :OUT        STD_LOGIC;
                n_sync        :OUT        STD_LOGIC;
                n_blank  :OUT        STD_LOGIC;
                VGACLK  :OUT STD_LOGIC
                );
               
END VGA;


ARCHITECTURE AA OF VGA IS
               
        SIGNAL  RESET : STD_LOGIC:='0';
       
          component PLL is port (
            clk_in_clk  : in  std_logic := 'X'; -- clk
            reset_reset : in  std_logic := 'X'; -- reset
            clk_out_clk : out std_logic        -- clk
        );
    end component PLL;
       
        COMPONENT VGA_CONTROLLER IS PORT(
                pixel_clk        :        IN                STD_LOGIC;        --pixel clock at frequency of VGA mode being used
                reset_n                :        IN                STD_LOGIC;        --active low asycnchronous reset
                h_sync                :        OUT        STD_LOGIC;        --horiztonal sync pulse
                v_sync                :        OUT        STD_LOGIC;        --vertical sync pulse
                disp_ena                :        OUT        STD_LOGIC;        --display enable ('1' = display time, '0' = blanking time)
                column                :        OUT        INTEGER;                --horizontal pixel coordinate
                row                        :        OUT        INTEGER;                --vertical pixel coordinate
                n_blank                :        OUT        STD_LOGIC;        --direct blacking output to DAC
                n_sync                :        OUT        STD_LOGIC); --sync-on-green output to DAC
               
        END COMPONENT;
       
        COMPONENT HW_IMAGE_GENERATOR IS PORT(
                disp_ena                :        IN                STD_LOGIC;        --display enable ('1' = display time, '0' = blanking time)
                COLUmn                :        IN                INTEGER;                --row pixel coordinate
                ROW                  :        IN                INTEGER;       
                red                        :        OUT        STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');  --red magnitude output to DAC
                green                        :        OUT        STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');  --green magnitude output to DAC
                blue                        :        OUT        STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0')); --blue magnitude output to DAC
        END COMPONENT;


                SIGNAL disp_ena        :        STD_LOGIC;
                SIGNAL row                        :        INTEGER;
                SIGNAL column                :        INTEGER;
                SIGNAL reset_n                :        STD_LOGIC;
                SIGNAL PIXel_clk        :  STD_LOGIC;
       
        begin


                VGACLK<=PIXel_clk;
               
                U1: PLL PORT MAP ( CLK, reset_N, PIXel_clk);
                u2: vga_CONTROLLER port map (pixel_clk, reset_N, h_sync, v_sync, disp_ena, COLUmn, ROW, n_blank, n_sync);
                u3: hw_IMAGE_GENERATOR port map (disp_ena,COLUmn, ROW, RED,GREEN,BLUE);


end AA;
and other codes
Code:
LIBRARY ieee;USE ieee.std_logic_1164.all;


ENTITY hw_image_generator IS
        GENERIC(
                pixels_y :        INTEGER := 478;    --row that first color will persist until
                pixels_x        :        INTEGER := 600);  --column that first color will persist until
        PORT(
               
                disp_ena                :        IN                STD_LOGIC;        --display enable ('1' = display time, '0' = blanking time)
                row                        :        IN                INTEGER;                --row pixel coordinate
                column                :        IN                INTEGER;       
                red                        :        OUT        STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');  --red magnitude output to DAC
                green                        :        OUT        STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');  --green magnitude output to DAC
                blue                        :        OUT        STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0')); --blue magnitude output to DAC
END hw_image_generator;


ARCHITECTURE behavior OF hw_image_generator IS
BEGIN
        PROCESS(disp_ena, row, column)
        BEGIN


                IF(disp_ena = '1') THEN                --display time
                        IF(row < pixels_y AND column < pixels_x) THEN
                                red <= (OTHERS => '0');
                                green        <= (OTHERS => '0');
                                blue <= (OTHERS => '1');
                        ELSE
                                red <= (OTHERS => '1');
                                green        <= (OTHERS => '1');
                                blue <= (OTHERS => '0');
                        END IF;
                ELSE                                                                --blanking time
                        red <= (OTHERS => '0');
                        green <= (OTHERS => '0');
                        blue <= (OTHERS => '0');
                END IF;
       
        END PROCESS;
END behavior;
Code:

LIBRARY ieee;
USE ieee.std_logic_1164.all;


ENTITY vga_controller IS
        GENERIC(
                h_pulse        :        INTEGER := 208;            --horiztonal sync pulse width in pixels
                h_bp                :        INTEGER := 336;                --horiztonal back porch width in pixels
                h_pixels        :        INTEGER := 1920;                --horiztonal display width in pixels
                h_fp                :        INTEGER := 128;                --horiztonal front porch width in pixels
                h_pol                :        STD_LOGIC := '0';                --horizontal sync pulse polarity (1 = positive, 0 = negative)
                v_pulse        :        INTEGER := 3;                        --vertical sync pulse width in rows
                v_bp                :        INTEGER := 38;                        --vertical back porch width in rows
                v_pixels        :        INTEGER := 1200;                --vertical display width in rows
                v_fp                :        INTEGER := 1;                        --vertical front porch width in rows
                v_pol                :        STD_LOGIC := '1');        --vertical sync pulse polarity (1 = positive, 0 = negative)
        PORT(
                pixel_clk        :        IN                STD_LOGIC;        --pixel clock at frequency of VGA mode being used
                reset_n                :        IN                STD_LOGIC;        --active low asycnchronous reset
                h_sync                :        OUT        STD_LOGIC;        --horiztonal sync pulse
                v_sync                :        OUT        STD_LOGIC;        --vertical sync pulse
                disp_ena                :        OUT        STD_LOGIC;        --display enable ('1' = display time, '0' = blanking time)
                column                :        OUT        INTEGER;                --horizontal pixel coordinate
                row                        :        OUT        INTEGER;                --vertical pixel coordinate
                n_blank                :        OUT        STD_LOGIC;        --direct blacking output to DAC
                n_sync                :        OUT        STD_LOGIC); --sync-on-green output to DAC
               
END vga_controller;


ARCHITECTURE behavior OF vga_controller IS
        CONSTANT        h_period        :        INTEGER := h_pulse + h_bp + h_pixels + h_fp;  --total number of pixel clocks in a row
        CONSTANT        v_period        :        INTEGER := v_pulse + v_bp + v_pixels + v_fp;  --total number of rows in column
BEGIN


        n_blank <= '1';  --no direct blanking
        n_sync <= '0';  --no sync on green
       
        PROCESS(pixel_clk, reset_n)
                VARIABLE h_count        :        INTEGER RANGE 0 TO h_period - 1 := 0;  --horizontal counter (counts the columns)
                VARIABLE v_count        :        INTEGER RANGE 0 TO v_period - 1 := 0;  --vertical counter (counts the rows)
        BEGIN
       
                IF(reset_n = '0') THEN                --reset asserted
                        h_count := 0;                                --reset horizontal counter
                        v_count := 0;                                --reset vertical counter
                        h_sync <= NOT h_pol;                --deassert horizontal sync
                        v_sync <= NOT v_pol;                --deassert vertical sync
                        disp_ena <= '0';                        --disable display
                        column <= 0;                                --reset column pixel coordinate
                        row <= 0;                                        --reset row pixel coordinate
                       
                ELSIF(pixel_clk'EVENT AND pixel_clk = '1') THEN


                        --counters
                        IF(h_count < h_period - 1) THEN                --horizontal counter (pixels)
                                h_count := h_count + 1;
                        ELSE
                                h_count := 0;
                                IF(v_count < v_period - 1) THEN        --veritcal counter (rows)
                                        v_count := v_count + 1;
                                ELSE
                                        v_count := 0;
                                END IF;
                        END IF;


                        --horizontal sync signal
                        IF(h_count < h_pixels + h_fp OR h_count >= h_pixels + h_fp + h_pulse) THEN
                                h_sync <= NOT h_pol;                --deassert horiztonal sync pulse
                        ELSE
                                h_sync <= h_pol;                        --assert horiztonal sync pulse
                        END IF;
                       
                        --vertical sync signal
                        IF(v_count < v_pixels + v_fp OR v_count >= v_pixels + v_fp + v_pulse) THEN
                                v_sync <= NOT v_pol;                --deassert vertical sync pulse
                        ELSE
                                v_sync <= v_pol;                        --assert vertical sync pulse
                        END IF;
                       
                        --set pixel coordinates
                        IF(h_count < h_pixels) THEN          --horiztonal display time
                                column <= h_count;                        --set horiztonal pixel coordinate
                        END IF;
                        IF(v_count < v_pixels) THEN        --vertical display time
                                row <= v_count;                                --set vertical pixel coordinate
                        END IF;


                        --set display enable output
                        IF(h_count < h_pixels AND v_count < v_pixels) THEN          --display time
                                disp_ena <= '1';                                                                                                --enable display
                        ELSE                                                                                                                                        --blanking time
                                disp_ena <= '0';                                                                                                --disable display
                        END IF;


                END IF;
        END PROCESS;


END behavior;
↧

plz help......Seqence recognizer error

June 9, 2018, 8:29 pm
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0
0
`timescale 1ns/ 1ps


module tb_seqrec;
reg rnRESET, rCLK, rX;
wire wZ;

seqrec seqrec0(.nRESET(rnRESET), .CLK(rCLK), .X(rX), .Z(wZ));


always
begin
#500 rCLK <= ~rCLK;
end

initial
begin
rnRESET <= 1'b0;
rX <= 1'b0;
19#100 rnRESET <= 1'bl;
20#1000 rX <= 1'bl;
21#1000 rX <= 1'bl;
22#1000 rX <= 1'b0;
23#1000 rX <= 1'b0;
24#1000 rX <= 1'bl;
25#1000 rX <= 1'bl;
26#1000 rX <= 1'b0;
27#1000 rX <= 1'bl; // Z=1
28#1000 rX <= 1'bl;
29#1000 rX <= 1'b0;
30#1000 rX <= 1'bl; // Z=1
31#1000 rX <= 1'b0;
32#1000 rX <= 1'bl;
end


endmodule


I made it. l thought there is no error.
but
:/Test/seqrec2/tb_seqrec.v(19): Expecting numeric digits.
** Error: C:/Test/seqrec2/tb_seqrec.v(19): near "1": syntax error, unexpected "IDENTIFIER", expecting ';'
** Error: C:/Test/seqrec2/tb_seqrec.v(20): Expecting numeric digits.
** Error: C:/Test/seqrec2/tb_seqrec.v(20): near "1": syntax error, unexpected "IDENTIFIER", expecting ';'
** Error: C:/Test/seqrec2/tb_seqrec.v(21): Expecting numeric digits.
** Error: C:/Test/seqrec2/tb_seqrec.v(21): near "1": syntax error, unexpected "IDENTIFIER", expecting ';'
** Error: C:/Test/seqrec2/tb_seqrec.v(24): Expecting numeric digits.
** Error: C:/Test/seqrec2/tb_seqrec.v(24): near "1": syntax error, unexpected "IDENTIFIER", expecting ';'
** Error: C:/Test/seqrec2/tb_seqrec.v(25): Expecting numeric digits.
** Error: C:/Test/seqrec2/tb_seqrec.v(25): near "1": syntax error, unexpected "IDENTIFIER", expecting ';'
** Error: C:/Test/seqrec2/tb_seqrec.v(27): Expecting numeric digits.
** Error: C:/Test/seqrec2/tb_seqrec.v(27): near "1": syntax error, unexpected "IDENTIFIER", expecting ';'
** Error: C:/Test/seqrec2/tb_seqrec.v(28): Expecting numeric digits.
** Error: C:/Test/seqrec2/tb_seqrec.v(28): near "1": syntax error, unexpected "IDENTIFIER", expecting ';'
** Error: C:/Test/seqrec2/tb_seqrec.v(30): Expecting numeric digits.
** Error: C:/Test/seqrec2/tb_seqrec.v(30): near "1": syntax error, unexpected "IDENTIFIER", expecting ';'
** Error: C:/Test/seqrec2/tb_seqrec.v(32): Expecting numeric digits.
** Error: C:/Test/seqrec2/tb_seqrec.v(32): near "1": syntax error, unexpected "IDENTIFIER", expecting ';'


what's wrong?
↧
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