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Problems trying to configure three FPGAS using the EPC16

June 14, 2018, 9:13 am
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The aim of this thread is to request help from you guys because I have a problem trying to make a .pof file which is driving me crazy.

I am working on a card which has three FPGA (each one running different configuration files), I produced the .sof files and I successfully tested programing the FPGA using a jtag cable.

Now I would like to create a .pof file (for keeping the new FPGA personality in the non-volatile flash, in this case an EPC16), here is where my problem starts...

Using the "convert programming files" tool I produced a .pof file from the three .sof files (one for each FPGA) but for a reason which I cannot understand the FPGAs are not programed (done line does not go high) when I power cycle the card.

Do you have a clue, suggestion or hint which allows me to get rid of this problem and finally produce a working pof for the EPC16?

Your help will be more than welcome!

some extra data:
The three FPGA should be programmed using the 1-bit passive serial mode
I am using Quartuss II, Version 11.0

attached you will find some screen captures that shows how I am using the "convert programming file" tool.
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SDC File rules for Synchronizers

June 14, 2018, 5:18 pm
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Hello All,
I feel like this question has been asked before but I must not be searching for the right keywords. Do here it goes again:

I have two clock domains in my design. One is the main system clock running at 200MHZ and the other is the ADC clock coming from the ADC running at 14.6MHZ. I use FIFOs to receive the data and pass it to the rest of the FPGA logic.

At some point, the FPGA logic needs to clear the fifo and other associated registers in the ADC clock domain. So I put a two stage synchronizer between the reset signal from the 200MHz clock domain and the ADC clock domain.

TimeQuest complains about not being able to meet timing into the first synchronizer stage register.

What is the best way to tell the timing analyzer tool that I have a synchronizer? I defined clock groups for my system clock and adc clock and that made the error go away but I'm afraid that will lead to an under constrained design and mask future problems.

Thanks,
-Ali
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Need SPI core variant advice - Altera FPGA development kit '3-wire DAC'

June 14, 2018, 5:52 pm
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I need to write to the 3 pin SPI DAC on Intel Max10 FPGA Development Kit from C using NIOS soft processor.
There are several SPI IP varieties to choose from in Platform Designer.
I'm not sure which SPI variant to choose and i'm not able to find a demo or documents/videos on this subject.
The DAC is the three pin SPI DAC, so I expect that the best choice is the 'SPI-(3 wire Serial)', but I would like to confirm this. Is this the logical choice?
What do you use most often? Example of typical code? Thanks for your help.

Bob
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About the LVDS output swing

June 14, 2018, 10:08 pm
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I choose a device，It's lvds output swing is from 250mV~450mV.
But the sink device is a 1.8V LVDS port which require swing from 100mV~300mV,
How can I connect these two devices？
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Serdes fitter placement ERROR in Quartus II 17.1

June 15, 2018, 1:55 am
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I got a fitter placement error in Quartus II 17.1 and the problem as below: SW VERSION: Quartus II 17.1 Device: 5CGTFD7D5F27C7 Background and problem: There are two serdes modules in our design, one is custom serdes IP with 1 channel. And another is RapidIOx2 IP. I would like to merge the TX PLL for the two Serdes modules in my design, so I follow the rules: Our Device is CycloneV GT D7(5CGTFD7D5F27C7) and serdes channel as below: One configuration can pass fitter: channel 0-> custom serdes; channel 1-> reserve for PLL; channel 2-> RapidIOX2[0]; channel 3-> RapidIOX2[1]; channel 4-> null; channel 4-> null; But this Configuration will fail at fitter (only difference is the pin assignment change on RapidIO) channel 0-> custom serdes; channel 1-> reserve for PLL; channel 2-> null; channel 3-> null; channel 4-> RapidIOX2[0]; channel 4-> RapidIOX2[1]. Where the RapidIO PLL should be merged with custom IP PLL and only one PLL placed at channel1. But now it seems they are not merged. The fitter error message as below: ----------------------------------------------------start of error message---------------------------------------------------------- "Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 Channel PLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/suppo...se/search.html and search for this specific error message number. Error (175020): The Fitter cannot place logic Channel PLL that is part of RapidIO (IDLE1 up to 5.0 Gbaud) srio_serdes_rapidio_0 in region (0, 19) to (0, 25), to which it is constrained, because there are no valid locations in the region for logic of this type. Info (14596): Information about the failing component(s): Info (175028): The Channel PLL name(s): srio_top:inst_srio_top|srio_serdes_ip:inst_sriox2| srio_serdes:inst_srio_serdes|srio_serdes_rapidio_0 :rapidio_0|srio_serdes_rapidio_0_rio:srio_serdes_r apidio_0_rio_inst|srio_serdes_rapidio_0_riophy_xcv r:riophy_xcvr|srio_serdes_rapidio_0_riophy_gxb:rio phy_gxb|altera_xcvr_custom:srio_serdes_rapidio_0_r iophy_gxb_inst|av_xcvr_custom_nr:A5|av_xcvr_custom _native:transceiver_core|av_xcvr_plls:gen.av_xcvr_ native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].pll.cmu_pll.tx_pll Error (16234): No legal location could be found out of 6 considered location(s). Reasons why each location could not be used are summarized below: Error (178004): Could not find location for the Channel PLL that enable routing of bonding clock lines (6 locations affected) Info (175029): Channel PLL containing CHANNELPLL_X0_Y13_N32 Info (175029): Channel PLL containing CHANNELPLL_X0_Y21_N32 Info (175029): Channel PLL containing CHANNELPLL_X0_Y25_N32 Info (175029): Channel PLL containing CHANNELPLL_X0_Y33_N32 Info (175029): Channel PLL containing CHANNELPLL_X0_Y37_N32 Info (175029): Channel PLL containing CHANNELPLL_X0_Y45_N32 Info (175013): The Channel PLL is constrained to the region (0, 21) to (0, 25) due to related logic Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/suppo...se/search.html and search for this specific error message number. Error: Quartus Prime Fitter was unsuccessful. 5 errors, 105 warnings Error: Peak virtual memory: 1899 megabytes Error: Processing ended: Fri Jun 15 12:09:28 2018 Error: Elapsed time: 00:03:30 Error: Total CPU time (on all processors): 00:03:30 Error (293001): Quartus Prime Full Compilation was unsuccessful. 7 errors, 1222 warnings" ----------------------------------------------------end of error message---------------------------------------------------------- So may I know how any way to make the second configuration work. Thx to all.
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Simulating Cyclone V altera_hps with ModelSim

June 15, 2018, 3:42 am
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Quartus 18.0 Standard, ModelSim Intel FPGA Starter Edition 10.5b.

Trying to simulate a design that contains a Platform Designer generated instance of altera_hps (for access to HPS-side DDR3 RAM via the FPGA to HPS bridge).

First I tried to follow the instructions from the Qsys/Platform Designer tutorial. I got Platform Designer to generate the simulation script, then fired up ModelSim and loaded it. It complained about MvcHome not being set, then gave me a few hundred errors of the kind

# ** Warning: (vsim-3770) Failed to find user specified function 'questa_mvc_sv_find' in DPI C/C++ source files.
# Time: 0 ps Iteration: 0 Region: /QUESTA_MVC File: ./soc_system/simulation/submodules/questa_mvc_svapi.svh
# ** Warning: (vsim-3770) Failed to find user specified function 'questa_mvc_sv_valid' in DPI C/C++ source files.
# Time: 0 ps Iteration: 0 Region: /QUESTA_MVC File: ./soc_system/simulation/submodules/questa_mvc_svapi.svh
# ** Warning: (vsim-3770) Failed to find user specified function 'questa_mvc_sv_advance' in DPI C/C++ source files.
# Time: 0 ps Iteration: 0 Region: /QUESTA_MVC File: ./soc_system/simulation/submodules/questa_mvc_svapi.svh
# ** Warning: (vsim-3770) Failed to find user specified function 'questa_mvc_sv_release' in DPI C/C++ source files.
# Time: 0 ps Iteration: 0 Region: /QUESTA_MVC File: ./soc_system/simulation/submodules/questa_mvc_svapi.svh


finished off by

# ** Fatal: (vsim-160) ./soc_system/simulation/submodules/mgc_common_axi.sv(3173): Null foreign function pointer encountered when calling 'axi_initialise_SystemVerilog'
# Time: 0 ps Iteration: 0 Process: /DE10_NANO_SoC_GHRD/u0/hps_0/fpga_interfaces/f2h_axi_slave_inst/axi/#INITIAL#3193 File: ./soc_system/simulation/submodules/mgc_common_axi.sv
# FATAL ERROR while loading design


As far as I could establish after a *lot* of digging (and correct me if I'm wrong), this requires a bus functional model (BFM) for the AXI bus, and it is not included in ModelSim Starter Edition and requires a separate paid license.

Abandoned this approach and tried to load simulation out of Quartus. Oddly, this time it tries to load sources from soc_system/synthesis/submodules instead of soc_system/simulation/submodules, which is why errors are different. After resolving most load failures, I end up with:

Loading soc_system.soc_system_hps_0
# Loading soc_system.soc_system_hps_0_fpga_interfaces
# ** Error: (vsim-3033) C:/Development/fpga/DE10_DDR3/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv(151): Instantiation of 'cyclonev_hps_interface_clocks_resets' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /DE10_NANO_SoC_GHRD/u0/hps_0/fpga_interfaces File: C:/Development/fpga/DE10_DDR3/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv
# Searched libraries:
# C:/intelFPGA/18.0/modelsim_ase/altera/verilog/altera_mf
# C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/altera_mf
# C:/Development/fpga/DE10_DDR3/simulation/modelsim/soc_system
# C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/cyclonev
# C:/intelFPGA/18.0/modelsim_ase/altera/verilog/cyclonev
# C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/altera_lnsim
# C:/intelFPGA/18.0/modelsim_ase/altera/verilog/cyclonev_hssi
# C:/Development/fpga/DE10_DDR3/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) C:/Development/fpga/DE10_DDR3/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv(170): Instantiation of 'cyclonev_hps_interface_dbg_apb' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /DE10_NANO_SoC_GHRD/u0/hps_0/fpga_interfaces File: C:/Development/fpga/DE10_DDR3/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv
# Searched libraries:
# C:/intelFPGA/18.0/modelsim_ase/altera/verilog/altera_mf
# C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/altera_mf
# C:/Development/fpga/DE10_DDR3/simulation/modelsim/soc_system
# C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/cyclonev
# C:/intelFPGA/18.0/modelsim_ase/altera/verilog/cyclonev
# C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/altera_lnsim
# C:/intelFPGA/18.0/modelsim_ase/altera/verilog/cyclonev_hssi
# C:/Development/fpga/DE10_DDR3/simulation/modelsim/rtl_work
...
and a bunch of others (e.g. cyclonev_hps_peripheral_emac and cyclonev_hps_peripheral_usb), 17 total.

None of those seem to be implemented in software or known to ModelSim.

Do I understand correctly that Cyclone V designs using altera_hps IP simply can't be simulated without paying more money for another license?

Some googling turned up the part number for the license that seems to be needed - IPS-AXIBFM ( http://www.alteraforum.com/forum/showthread.php?t=42038 ) - and it is $495 on Mouser. Seriously? I paid $130 for the board ...
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SignalTap problem with SoCFPGA configured by HPS

June 15, 2018, 3:52 am
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Hi,
I have a problem using SignalTapII that occurs when the FPGA is configured by HPS.

I have a design with u-boot bootloader and custom linux with drivers handling my FPGA IPcores.

When I:
1) pause u-boot; 2) load fpga from sof file with blaster; 3) boot linux from command line;
everything works OK and i can hook up the SignalTapII and look at the signals.

When I load the fpga with u-boot script from rbf file, my design:
a) behaves little bit different (some reset issues? I Don't Know)
b) I cannot hook up the SignalTapII connection. SignalTapII shows "Not compatible with the device" and "Program the device and continue"

I generate rbf file with "File->convert programming file..." option in quartus

Have You got any ideas what could go wrong?
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Instantiating VHDL entity in Systemverilog

June 15, 2018, 9:26 am
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I am trying to instantiate a VHDL entity in systemverilog. In the VHDL entity “iobits” is defined as follows.
 iobits : inout std_logic_vector (67 downto 0);
because I am interfacing to a DE10_Nano to an external PCB that has lines connected out of sequential order compared to the GPIO lines that are expected, I need to connect the iobits to GPIO individually.
In systemverilog I have defined GPIO as
inout wire [35:0] GPIO_0,
inout wire [35:0] GPIO_1,
So I need to connect
iobits[0] to GPIO_0[16],
Iobits[1] to GPIO_0[17],
iobits[2] to GPIO_0[14],
etc.

I tried several different things but keep getting syntax errors.
Help!!!

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Problem with transferring data from different clock domains using dual_port_ram

June 15, 2018, 9:36 am
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Hello everyone,
I want to transfer a frame from 143Mhz clock domain to 49Mhz clock domain to view the frames through vga,
For a test i tried to transfer a vertical and horizontal white lines to view through the vga port. But i am not getting it right. What i expect is https://ibb.co/inK4qJ . But what i am getting is https://ibb.co/i3hojd . I don't know what i have done wrong. I am stuck
here, If someone could help me, it would be great.

Thank you!

(All the VHD files are uploaded and the top level is "fifo.vhd". The board i am using is DE1-SoC)
Attached Files
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5AGXFB3H4F35C5NES device support

June 15, 2018, 9:53 am
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I have an Arria V GX starter kit (Engineering Sample), so the exact device number is 5AGXFB3H4F35C5NES.
However, there is no such device support in my quartus prime software.
I have the quartus prime 18.0.0.614 standard edition, with support for the Arria V family installed.
The closest device number I have found is 5AGXFB3H4F35C5 (there are no 'N' or 'NES' options at the end), and I have chosen that for my project.
When I try flashing my FPGA dev board, there are compatibility issues.

Is there any way I can install support for my particular device? Or does this version of quartus not support the ES (Engineering Sample) version of this board anymore?

I would really appreciate some feedback. Thank you.
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Win10 crashes with USB Blaster - any patch available?

June 15, 2018, 10:09 am
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Tried it with Quartus 17 and 18. When opening the tools -> programmer it doesn't recognize the USB blaster, after 'Hardware Setup" it hangs up for a minute it recognize it but when connecting to proven board the windows crashes.

Same behavior on differn computers (both with Win10) and with different USB Blasters....

I remember that long time ago there was similar issue, then the solution was by re-installing an older version driver.
Is there any solution now?
Any usable link to different driver?
Meantime i'm stuck....

Thanx,
Eli.
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What is the best way to generate multiple clocks with minimum jitter and delays?

June 15, 2018, 10:28 am
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Hi,

I have to generate several clocks on Arria 10 SoC board. The clocks and their applications are as follows:
  1. 3GHz clock: for clocking external ADC to sample the incoming data, and receive it at transceiver pins using JESD204B IP.
  2. 1.5GHz clock: to transmit the data from transceiver pins using Transceiver PHY IP (PMA width = 10)
  3. 150MHz clock: to clock the coreclock of Transceiver PHY for transmitting data at 1.5GHz


I think I have two options: 1) instantiate several PLLs and 2) generate 3GHz clock using fPLL from the 50MHz reference clock and use counters to create lower-frequency clocks. The first option does not seem to be good as each PLL would have its own locking time and would be located at different places, which would add phase delays due to route lengths. For the second option, I am not sure how reliable the counter would be while running at 3GHz.

Please suggest what would be the best way to generate the above-frequency clocks so that they have minimum phase delay and jitter?

Thanks,
Arvind
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EPE Early Power Estimator

June 15, 2018, 12:26 pm
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EPE Early Power Estimator Excel file doesn't allow me to change VOD setting from 31 to any other number through Transceiver section of Cyclone 10 GX EPE.

The message I am getting is

" The cell or chart you are trying to change is on a protected sheet. To make a change, unprotect the sheet. You might be requested to enter a password"

Then I went to "Review" section of Excel by clicking Review on the top center of Excel Program. Then I selected "Unprotect Sheet". The excel asked to enter password.

I don;t know the password :)
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Interface SD Card through GPIO on DE0-Nano

June 15, 2018, 1:24 pm
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I would like to interface my Terasic DE0-Nano running a Cyclone IV with an external SD card that I will attach to a circuit board that will also interface with the GPIO headers on the DE0. I'm pulling in multiple (>20) lines of binary data at approximately 160 kHz and would like to save it to an SD card that a Raspberry Pi will also have access to. The end product will essentially have the FPGA running independently of the RPi, which will periodically pull off data that the FPGA generates. Could someone please point me in the right direction as to how to do this?

Thanks in advance.
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Quartus Editing Features - Find in Files & Find by Reference

June 15, 2018, 3:14 pm
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In trying to learn about SystemVerilog and start using it in design over Verilog there comes the idea of greater abstraction by making use of typedef, structs, interfaces, and packages. This is great for readability and shortening code, but a disadvantage of this is that when you need to remind yourself what was in that typedef you need to reference the definition. If that definition is used in multiple spots it will likely be located in a package and depending upon how you break things out you need locate the file, then the definition line.

As far as I can tell Quartus II does not allow for the ability to search for a string in all project files. You can search for a string in a file or all open files, but it will not search in all directory paths that are in the project. Nor upon compilation of the project will the user defined objects be searchable for their reference/definition at all.

Are these features supported in Quartus II in some abstract way or are they really not available? The alternative methods I thought of doing was to link an external text editor that would support at least the function of find in all files. However, doing the find by reference would require a parser to search through user defined types to find where the definitions are and such. Another method I thought of was maybe leverage a TCL file and just make the parser myself, but I am not sure if that could work.
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Bi-direction signal issues

June 15, 2018, 5:42 pm
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Hi Guys,

I met an issue for Bi-direction signals. When the state is for output from FPGA, the data is not correct... Please help me.

So I have a top module and connect the inouts to a submodule, and the value assignment is in the submodule. Will this be an issue?

Here is part of the code:

entity top is
port(
clk : in std_logic;
nRst : in std_logic;

emif_cs_n : in std_logic;
emif_R_nW : in std_logic;
emif_addr : inout std_logic_vector(9 downto 0);
emif_data : inout std_logic_vector(7 downto 0)
);
end top;


architecture behavior of top is


component sub is
port(
nRst : in std_logic;
clk : in std_logic;


emif_cs_n : in std_logic;
emif_R_nW : in std_logic;
emif_addr : inout std_logic_vector(9 downto 0);
emif_data : inout std_logic_vector(7 downto 0)
);
end top;


sub_u: sub
port map(
nRst => nRst ,
clk_100M => clk_100M ,


emif_cs_n => emif_cs_n ,
emif_R_nW => emif_R_nW ,
emif_addr => emif_addr ,
emif_data => emif_data ,
);


end behavior;
------------------
entity sub is
port(
nRst : in std_logic;
clk_100M : in std_logic;
--emif
emif_cs_n : in std_logic;
emif_R_nW : in std_logic;
emif_addr : inout std_logic_vector(9 downto 0);
emif_data : inout std_logic_vector(7 downto 0)
);
end sub;

emif_data <= rdata_reg when (rd_period = '1') else (others => 'Z');
emif_addr <= raddr_reg when (emif_cs_n = '0' and emif_R_nW = '1') else (others => 'Z');
----------------
here is from signaltap


So what causes the bi-direction signals not following the register value?

The condition haven't changed during the time, meaning always outputting data.
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Spectrum analyzer

June 16, 2018, 6:42 am
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Hi,
I'm fairly new at this and was wondering if someone could tell me how to implement a spectrum analyzer on the de0-nano-soc using lt24 and a daughter board to take in an analog signal. I have no idea where to start or how to implement this design. A step by step would be very helpful.
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Why should I learn Qsys/Platform Designer

June 16, 2018, 11:21 am
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I've created digital designs for 5+ years. I have never used Qsys. I've written HDL modules, manually wired them, did timing analysis and eventually synthesize them. I never found the need to use Qsys.

Am I missing out on any benefits?
Why should I use Qsys?
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Implementing a Large RAM on Cyclone II - is it possible?

June 16, 2018, 2:07 pm
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Hi, this is my first time implementing something on FPGA.
My instructor is currently very busy and I can't find an answer to my problem, hoped I would find here someone nice enough to help.

In an architecture I need to implement there is a 64X1006 (can be larger of course) bit addressable array.

When I designed the architecture I didn't know the capabilities of the FPGA, but now when I want to implement it I've seen that the blockrams are of size of 4K bits...

As to the number of ports:
Dual write can greatly enhance the performance, but I can manage just fine with a single write per cycle.
Read is always single read per cycle.

The device I'm using is Cyclone II EP2C35F672C6 which seems to contain M4K blocks

Is there any way I can implement this entirely on the FPGA? External dual-port RAM seems to me too exotic, and also I'm not sure if I'm allowed to use even a regular, single-port one.

Thanks in advance to those who are willing to answer or to direct me to an answer.

Dan
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(Quartus 17.1) Missing pin assignments for input/outputs in schematic files (.bsf)

June 16, 2018, 6:48 pm
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Hello,

since I started to use 17.1 lite edition, I am not able to see the assigned pins for all inputs/ outputs in the block schematics of my projects anymore. I would like to see which output is connected to which pin in my schematic file (.bsf). Even when I create new projects from scratch, I am not able to see the assignments I have done earlier with the Pinplanner in my project which should be transfered and visualized in the current schematic (.bsf)-file, although all assignments are preserved in the "assignment editor" and "Pin Planner". Actually, I can resolve this issue by using Quartus 15.1.....:confused:

How can I solve that problem?
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