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SR latch test bench help

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Hey im not sure how to make a testbench for an sr latch, the code ive made is shown below for the latch and the testbench.

for the latch

library ieee;
use ieee.std_logic_1164.all;


entity tut6a is
port (
end tut6a;


architecture struct of tut6a is
signal r1 , s1, qa , qb : std_logic;
attribute keep : boolean;
attribute keep of r1 , s1 , qa , qb : signal is true;
begin


r1 <= r and clk;
s1 <= s and clk;
qb <= not (r1 and qa);
qa <= (s1 and qb);
q <= qa;


end struct;

for the testbench

library ieee;
use ieee.std_logic_1164.all;


entity Testbench6a is
end Testbench6a;


architecture struct of Testbench6a is
component tut6a
port ( clk , r , s : in std_logic;
qa , qb , rl , sl : out std_logic);
end component;
signal s , r , q : std_logic := '0';
signal rl , sl , qa , qb : std_logic := '0';
signal clk : std_logic := '1';
begin
inst1 : tut6a port map( clk ,
r ,
s ,
qa,
qb,
rl,
sl );
process
begin


s <= '1';
r <= '0';
wait for 10 ns;
s <= '0';
r <= '1';
wait for 10 ns;
s <= '1';
r <= '1';


wait for 10 ns;
end process;
end architecture;

Cyclone IV EP4CE10E22 circuit examples

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Hi,

I am making a circuit based on Cyclone IV FPGA (EP4CE10E22).

1) Is it possible to find schemes for JTAG interfacing?
2) Does this FPGA have an internal configuration memory? If an external memory is to be inserted, which is recommended and a reference scheme exists?
3) The package type is a E144. It is equivalent to QFP144?

Cyclone IV FPGA (EP4CE10E22) circuit

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Hi,

I am making a circuit based on Cyclone IV FPGA (EP4CE10E22).

1)
Is it possible to find schemes for JTAG interfacing?
2) Does this FPGA have an internal configuration memory? If an external memory is to be inserted, which is recommended and a reference scheme exists?
3) The package type is a E144. It is equivalent to QFP144?

Fast FPGA to HPS data transfer (write on RAM ?) on De0-Nano-SoC kit

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Hi everyone,

I'd like to send data, acquired by the FPGA, to the HPS. The HPS will then send these data to a computer, using ethernet.
The problem is the FPGA to HPS part needs to be really fast (around 100-150 MBytes/s).

I figured out the best way to do it would be to for the FPGA to write these data in the HPS RAM, then the HPS could simply read and send them to the computer.

Though, I haven't find a way yet to write in RAM from the FPGA, as the RAM is a HPS-connected peripheral.

Do you have any advice ?

Thanks a lots in advance.

de0 Nano ADC interfacing

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Hi all,

Im trying to interface with the ADC on the de0 nano, with a simple program to start with:
-Turn on LEDs if ADC value > 1.5V
-Turn off LEDs if ADC value <= 1.5V

It seems that I have something fatally wrong with my program, as my LEDs get turned on every time with 0V going into the adc. They even turn on if I flip the < and >= sign; meaning something must be very wrong indeed.

The following snippits are all from the same Module, which compiles and transfers fine to the fpga
Im using page 3 of this document as a reference:
ftp://ftp.altera.com/up/pub/Altera_M...0-Nano_ADC.pdf


I basically have three "events":
-Posedge of master clock: (1) generate clock signal for adc, manage cs signal going to adc
-posedge of adc clock: (1)write led values (2) read adc bits
-negedge of adc clock: (1) write adc channel number to adc

First, the inputs/outputs and the local vars:
Code:

module blinky2 (input clk,
                      output reg [7:0] led, //output to led
                      output reg sclk, //clock signal for adc, generated by this module
                      output reg cs=1, //communication channel to adc,
                      input dout, //data from adc
                      output reg din); //communication to adc, for channel selector
//local variables
    reg [24:0] counter=1;
    reg [5:0] adcClkCycNum=0;//the adc cycle number, 16 step process.
    reg [2:0] adcChNum=0;//the ADC channel number for use with din; set to 0 for now
    reg [12:0] adcSample=0;//12 bits for storing the digitized adc sample


Next, the generation of the sclk signal, which is the clock signal provided to the adc:
Merged into this is also management of the CS signal, which needs to be changed on both the positive and negative edge of the adc clock signal (so we manage it here, instead of on posedge/negedge of adc clock signal.
Code:

always @ (posedge clk)
begin
if (counter == 1)
    begin
    counter <= 25; //dividing the master clock clk by 25 to generate adc clock signal
    if (adcClkCycNum == 0) //cs must be set low on the lower edge of cycle 0
        begin
        if (sclk == 1)
            begin
            cs<=0;
            end
        end
    if (adcClkCycNum == 15)//cs must be set high on the rising edge of cycle 15
        begin
        if (sclk == 0)
            begin
            cs<=1;
            end
        end
    sclk <= ~sclk;
    end
else
    begin
    counter <= counter -1;
    end
end


Next, the things that happen on the positive edge of the adc clock:
This includes reading the sample from the adc, and setting the LEDs
Code:


always @ (posedge sclk)
    begin
        if (adcClkCycNum == 0)
            begin
            if (adcSample==150)
                begin
                led<=250;
                end
            adcClkCycNum<=1;
            end
        if (adcClkCycNum == 1)
            begin
            adcClkCycNum<=2;
            end
        if (adcClkCycNum == 2)
            begin
            adcClkCycNum<=3;
            end
        if (adcClkCycNum == 3)
            begin
            adcClkCycNum<=4;
            end
        if (adcClkCycNum == 4)
            begin
            adcSample[11]<=dout;
            adcClkCycNum<=5;
            end
        if (adcClkCycNum == 5)
            begin
            adcSample[10]<=dout;
            adcClkCycNum<=6;
            end
        if (adcClkCycNum == 6)
            begin
            adcSample[9]<=dout;
            adcClkCycNum<=7;
            end
        if (adcClkCycNum == 7)
            begin
            adcSample[8]<=dout;
            adcClkCycNum<=8;
            end
        if (adcClkCycNum == 8)
            begin
            adcSample[7]<=dout;
            adcClkCycNum<=9;
            end
        if (adcClkCycNum == 9)
            begin
            adcSample[6]<=dout;
            adcClkCycNum<=10;
            end
        if (adcClkCycNum == 10)
            begin
            adcSample[5]<=dout;
            adcClkCycNum<=11;
            end
        if (adcClkCycNum == 11)
            begin
            adcSample[4]<=dout;
            adcClkCycNum<=12;
            end
        if (adcClkCycNum == 12)
            begin
            adcSample[3]<=dout;
            adcClkCycNum<=13;
            end
        if (adcClkCycNum == 13)
            begin
            adcSample[2]<=dout;
            adcClkCycNum<=14;
            end
        if (adcClkCycNum == 14)
            begin
            adcSample[1]<=dout;
            adcClkCycNum<=15;
            end
        if (adcClkCycNum == 15)
            begin
            adcSample[0]<=dout;
            adcClkCycNum<=0;
            end
           
       
    end


And finally, the events that occur on the negative edge of the adc clock:
This includes sending the adc channel number to the adc in steps 2-4
Code:

always @ (negedge sclk)    begin
        if (adcClkCycNum == 0)
            begin
           
            end
        if (adcClkCycNum == 1)
            begin
           
            end
        if (adcClkCycNum == 2)
            begin
            //adc channel number, addr2
            din<=adcChNum[2];
            end
        if (adcClkCycNum == 3)
            begin
            //adc channel number, addr2
            din<=adcChNum[1];
            end
        if (adcClkCycNum == 4)
            begin
            //adc channel number, addr2
            din<=adcChNum[0];
            end
        if (adcClkCycNum == 5)
            begin
           
            end
        if (adcClkCycNum == 6)
            begin
           
            end
        if (adcClkCycNum == 7)
            begin
           
            end
        if (adcClkCycNum == 8)
            begin
           
            end
        if (adcClkCycNum == 9)
            begin
           
            end
        if (adcClkCycNum == 10)
            begin
           
            end
        if (adcClkCycNum == 11)
            begin
           
            end
        if (adcClkCycNum == 12)
            begin
       
            end
        if (adcClkCycNum == 13)
            begin
           
            end
        if (adcClkCycNum == 14)
            begin
           
            end
        if (adcClkCycNum == 15)
            begin
           
            end
    end

Ive got all the pinouts selected per the Altera manual.

My guess is that I have many things fatally wrong with this program. This is my first time trying to interface with an adc.
Any suggestions?

Thanks all

max10 - external reset

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Hi all,

Anyone know a good external PMIC reset device for the Max10? Preferably one with either a watchdog and / or manual reset. Perhaps a little late to the party but after moving from Altera to Lattice, primarily due to the MachXO2 line, I'm now happy to find out that the Max10 is a solid (and cheaper!) alternative. Now if only they came on 100pin TQFP packages.... :-0

-Mux

Encryptd altera library mapped Empty

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when we used modelsim 10.4b altera started edition in linux,the cyclonev_hssi_ver is mapped Empty in the tool library option.When we located the cyclonev_hssi_ver in src/verilog we find that it is the encrypted mentor library files are compiled in the directory but unable to map in the tool and we are unable to use the library in the code.

Please provide feedback.

nStatus held low Cyclone IV EP4CE6E22

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Hi,

I've designed a board with a Cyclone IV EP4CE6E22.
I have a problem with the config on the JTAG chain. My device is not detected.
I've checked all Vcc (I/O=3.3V, PLLA = 2.5V, VccINT= 1.2V) ;
nConfig is high but nStatus held low.
I have 10k pull-up (Vcc 3.3V) on this pin.

I don't understand what is my problem.

Please, help me.

Thanks
Alain

avalon ST video protocol hard time

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Hi everyone,
i'm working on arria10 soc board and i try to display a video that comes from a gigabit ethernet link and a 640x512 24b (8 bits per pixels + 3 color planes) rgb custom camera. For the moment, i don't use DDR4 for image buffering.
Instead i use a huge 2 ports on-chip memory for test (1310720 bytes). ( slave0 -> ram to dma interface(clock 148.5 MHz), slave1 -> camera rgb pixel (clock 125MHz))
I have a state machine that writes pixel data to this RAM on slave1 side while there is a DMA (university program one, consecutive addressing) that reads (slave0) this RAM
The vip mixer has 2 input : 1) 640*512 test pattern generator color bars 2) DMA

In my C program, i start IPs in this order 1)cvo 2)mixer 3)test pattern 4)dma
For the moment, i can display the color bars but as soon as i start the DMA, it disappears and only back ground from mixer is shown.

My questions are :
1- do i have to write a st control packet to ram firstor it's generated by dma itself?
2- if yes, is this control frame sequence valid?
sof + data_to_stvideo <= x"00000" & "1111"
data_to_stvideo <= x"00" & Iwidth(7 downto 4) & Iwidth(11 downto 8) & Iwidth(15 downto 12)
data_to_stvideo <= x"00" & Iheight(11 downto 8) & Iheight(15 downto 12) & Iwidth(3 downto 0)
data_to_stvideo <= x"00" & Interlacing_nibble & Iheight(3 downto 0) & Iheight(7 downto 4)
2- I write pixel data to ram like this but i'm not 100% sure : data_to_ram(31 downto 24) <= (others => '0') and data_to_ram(23 downto 0) <= red&green&blue and i increment address on next pixel

thank you for anything that can help me

Timing issues between D5M camera module and PIOs buttons in NIOSII SBT

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Hello everyone
I am of course no vice specially in timing the design. Kindly refer to the snapshot of my qsys system. This is in short a video capture system using D5M CMOS camera on DE-4 board. Video capture works pretty fine. The problem I face is in Software side and not in Hardware side. I mean in NIOS eclipse environment with C language, when I press pioButton have no effect i.e. code which is expected to run is not running. But when I press Hardware reset, very quickly after pressing reset the pioButton works fine. And as soon the video capture is started and getting displayed again on screen, the pioButton again goes like dead.

In simple words Video capture + display is working like mutually exclusive with pioButton. Either of these two may work. Once video capture is started PioButton have no effect.

All the connections are very well clear in snapshot. Other details:

DDR2 memory device speed grade is 533.333MHz; in general settings speed grade is 2; Memory clock frequency is 400MHz; PLL reference clock frequency is 50MHz; then you may see afi_clk is connected to all IPs except PIOs which are connected to 10MHz clock derived from pllInternal alt_pll IP.
Avalon MM-Clock crossing bridge master clock is connected to 10Mhz from alt_pll and slave clock with afi_clk of DDR.

My question is: Is there any necessary IP I must use to synchronize the events of PIOs and camera module (inculdes IPs Terasic_Camera, FrameBuffer, and Clocked Video Output)?
Or clocks distribution I am providing is wrong?

NOTE: C language code have no problem as I have tested the code running smoothly when after removing the Camera module which means disabling the camera and video capture gives no problem in Software at all.

Thanks a lot in advance. Snapshot is below:
Attached Images

Error: L6366E: my_strcopy.o attributes are not compatible with the provided attribute

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Hello,

I’m working on cyclone V based project using DS-5 AE tools.
I created a project using the Altera-Cyclone-V_RAM example of the DS-5 Examples & Programming Libraries’
The project compiles well and I can debug it without problem.
Then I created the assembler file according to the following example:
https://developer.arm.com/products/s...piler-features

This example is very simple and the file my_strcopy.s contains the following code:
PRESERVE8
AREA SCopy, CODE, READONLY
EXPORT my_strcopy ; Export symbol
my_strcopy ; R0 -> dest string
; R1 -> source string
LDRB R2, [R1],#1 ; Load byte + update addr
STRB R2, [R0],#1 ; Store byte + update addr
CMP R2, #0 ; Check for null
BNE my_strcopy ; Keep going if not
BX lr ; Return
END


When I compile the project I got the following error message:

armlink --cpu=Cortex-A9.no_neon.no_vfp --fpu=vfpv3 --scatter="../scatter.scat" --info=sizes -o"../Hello_and_ASM.axf" ./hello.o ./my_strcopy.o
Error: L6366E: my_strcopy.o attributes are not compatible with the provided attributes.
Object my_strcopy.o contains Build Attributes that are incompatible with the provided attributes.
Tag_THUMB_ISA_use = No Thumb instructions were permitted to be used (=0)
Tag_Advanced_SIMD_arch = Use of the Advanced SIMD Architecture (Neon) was permitted (=1)
Finished: 3 information, 0 warning and 1 error messages.


What can I do?
Thanks for your Help
Kind regards
Jerome

Preloader Make untar failing.

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I am attempting to compile a new preloader on windows using SOCEDS 18.0...but am failing at untar'ing the uboot-socfpga.tar.gz.


Chris@DESKTOP-NSSUV7O /cygdrive/f/VirtualBox VMs/share/rocketboards_image/17_1_DE10/DE0_NANO_SOC_18_0/software/spl_bsp
$ make
tar zxf /cygdrive/c/intelFPGA/18.0/embedded/host_tools/altera/preloader/uboot-socfpga.tar.gztar: Error opening archive: Failed to open '/cygdrive/c/intelFPGA/18.0/embedded/host_tools/altera/preloader/uboot-socfpga.tar.gz'
make: *** [uboot-socfpga/.untar] Error 1

Ideas?
Besides the point, I am trying to change the SOC Workshop Kernel Module #9 to use the FPGA 2 SDRAM instead of the FPGS 2 HPS (Heavyweight), by recompiling the preloader, as I've read this is why the FPGS 2 SDRAM is failing for me.

Right now I'm reinstalling SOCEDS into virtual machine, and trying again.
Project compiled with 18.0. SOCEDS is version 18.0


Thanks!

Qsys Avalon MM Slave needs a slower clock. Best way to do this?

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I’m modifying an existing Cyclone V Qsys design which is clocked from the HPS H2F user clock at 100 MHz . I need to add an Avalon Bus slave core to this system which requires a 50 MHz interface. It appears this will need it’s own 50 MHz clock reset, clock and Avalon MM bridge to interface to this my slave core. Is this correct or is there a better way to connect this?

Thank you for your attention

Data Transfer from FPGA-to-HPS

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Hi Everyone,

To give some background here is what I am currently working on, what hardware I have, and what I am trying to implement to solve my issue.
Board: DE0-Nano-SOC 5CSEMA4U23C6

Issue: I will be receiving around data into the FPGA at 40MHz. I need to make this data available to the HPS. The data will be ready in around 37KB chunks, I am planning on using a double buffer system so say we need a 75KB space to store said data. My idea is that I will stream the data in, fill up the buffer, signal the HPS that it is ready, the HPS will read the data, package it, and send it over an Ethernet network. I have actually asked this question in another part of the forum here: https://alteraforum.com/forum/showth...654#post239654, but realized this section would be better suited to the question. Going off what was talked about there, I am trying to get the FPGA-HPS bridge working in order for the FPGA to write to the HPS's DDR3 RAM and then have the HPS read from it. I have set the board up from the QSYS side correctly I believe. I limited the HPS RAM for linux to 800 MB. Then I have been trying to write to address 0x32000000, with absolutely 0 luck in getting anywhere. I am not sure if I am setting up something wrong in Quartus, my C code, or some other issue. And would appreciate any assistance in this.
Thanks!
-Andrew

EDIT: Currently I am using Linux, but I would eventually like to move to BareMetal, for now though I am sticking with Linux.

New thread Lost

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Hi all,

I just posted a new thread titled "License File for Purchased IP" in the General discussion forum. After I hit submit new thread, the system brings me back to the forum listing, not the new post. I searched this title and found no matched result; looked at my posting history but again nothing. I tried to post the same thread with the same title, the system says this is a duplicate post and declines.

So where is this new post then? This is strange.

Ben

License File for Purchased IP

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Hi all,

Recently I purchased IPS-EMBEDDED from Mouser Electronics, which is supposedly the base IP suite (include ddr memory controller, 3-speed ethernet, etc.). Altera emailed me a product activation code and some vague instructions on how to obtain license files through Self Service Licensing centre.

The problem is that when I logged onto mySupport, the self service licensing page is empty (no products shown), and there is no way to specify the product I need to add. I also used the search button with the provided product activation code, but the system cannot process it.

I filed a service request 5 days ago, first they complained about me not using a work email. After updating my company information, I have not received any acknowledgement. I suspect that no one has looked at my service request yet.

The reason I post this question: I suppose there is something basic that I miss; the instructions on how to use a purchased IP should be intuitive or well-documented. I hope someone with experience dealing with Altera licenses can point me in the right direction.

Ben Chang

Problem with Max 10 I've never seen before

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I have an issue with a MAX 10 design. I've never seen this problem before and I am baffled by it. I have down loaded the FPGA image, which includes a NIOS, and user application code to the internal flash memory. I generated a .hex file from the application code and created a combined .pof and programmed the CFM and UFM using the USB Blaster. After programming the device, I can verify the its programmed before and after cycling power. The application will execute after reset has negated while I have the board powered up on the bench. However, after installing the board in the system which it needs to function in. The system will come up and access the board to run its power-on tests. Somewhere in that time, the flash memory will be corrupted or altered in someway where is will not function. I can remove the board and return it to the bench and I can't verify either the CFM or UFM using the device programming tool. The device memory is not blank but it fails to verify. I can reprogram the device again but eventually, the device will suffer from the same problem again. When the board does retain it's configuration, it will function properly and the application runs without any exceptions and will continue to operate as long as it is powered up. This problem doesn't occur everytime and it is occurring on multiple boards of the same design. Any ideas, questions or suggestions? Thanks.

How to design ALM for Aria 10?

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I have two simple 5-input and 3-input functions in Verilog.

Function 1: 3:1 Multiplexer
input a,b,c;
input [1:0] s1;
output wire east;


Function 2 : 2:1 Multiplexer
input d,e;
input s2; //sel line
output wire south;

Multiplexers are written with Case statements.
When I try so synthesize it in Altera with Aria - 10 FPGA selected. This gets mapped to 2-ALMs.

But I saw in datasheets that only 1-ALM is required to implement a 5-input and 3-input functions.
How do I force the ALM to map this logic in one Cell.

Why address space bytes allocated by QSYS does not match the SPI IP core ?

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Hello everyone:
I have a question: Why QSYS automatically allocates address space bytes that do not match the number of internal register address space bytes defined by the SPI IP core?
Specific use is as follows:
I use SPI(3wire serial)IP in QSYS (Quartus II 11.1sp2) ,Parameter settings see Figure 1, after the completion of the set up, use "Assign Base Addresses " function,but the number of bytes that QSYS automatically allocates is only 8 bytes(see Figure 2), it not match the register map of SPI IP core define.(see Figure 3).
In addition,when the data width of the master port (Avalon MM) is 8 bits, no matter how the SPI sets the data bit width, the number of bytes that QSYS automatically allocates is 8 bytes.When the data width of the master port (Avalon MM) is 16 bits, no matter how the SPI sets the data bit width, the number of bytes that QSYS automatically allocates is 16 bytes,and so on.
My question is :
When the number of bytes that QSYS automatically allocates is 8 bytes,Which byte is the specific address of the "rxdata ",''txdata","status","control" and "slaveselect" register?
Looking forward to your answer, thank you very much!
Attached Images

About path delay in my FPGA

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My dear,
My application is that a signal EN_in to my FPGA , and a EN_out from my FPGA to ADCs. Now I want to delay the signal for unknown ns to need the ADC timing,the detail ns is test by my teamer. So I set some deifferent paths and a probe IP in my design,so my teamer use the probe IP to select the best delay path to use.
--------------------------------------------------------------------------------
my design(.v):

input EN_in;
output EN_out;

(* keep *) wire EN_delay0;
(* keep *) wire EN_delay1;
(* keep *) wire EN_delay2;
(* keep *) wire EN_delay3;

assign EN_delay0 = EN_in;
assign EN_delay1 = EN_in;
assign EN_delay2 = EN_in;
assign EN_delay3 = EN_in;
assign EN_out = (probe==2'b00) ? EN_delay0 : ((probe==2'b01) ? EN_delay1 : ((probe==2'b10) ? EN_delay2 : EN_delay3));
--------------------------------------------------------------------------------
my constraint(.sdc):

set_min_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay0}] 1.000
set_max_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay0}] 2.000
set_min_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay1}] 3.000
set_max_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay1}] 4.000
set_min_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay2}] 5.000
set_max_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay2}] 6.000
set_min_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay3}] 7.000
set_max_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay3}] 8.000
--------------------------------------------------------------------------------

But,but...but...I found that 4 delay paths not work efficiently... There is just 570ns between The Max delay path and The Min delay path . And the min delay path isnot EN_delay3 .
My FPGA is EP4SGX230KH40. Help me.
Thanks all.
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