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QII 17.1 tristate controller IRQ -1 problem

June 19, 2018, 2:06 am
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Hello!

I use Quartus II 17.1 Standard edition with Stratix IV device. I have to connect LAN91C111 device. I use QSYS with altera_generic_tristate_controller for it.
After generation system.h file for embedded software development:

#define ALT_MODULE_CLASS_Lan_controller altera_generic_tristate_controller
#define LAN_CONTROLLER_BASE 0x10000
#define LAN_CONTROLLER_IRQ -1
#define LAN_CONTROLLER_IRQ_INTERRUPT_CONTROLLER_ID -1
#define LAN_CONTROLLER_IS_ETHERNET_MAC 1
#define LAN_CONTROLLER_LAN91C111_DATA_BUS_WIDTH 16
#define LAN_CONTROLLER_LAN91C111_REGISTERS_OFFSET 768
#define LAN_CONTROLLER_NAME "/dev/Lan_controller"
#define LAN_CONTROLLER_SPAN 65536
#define LAN_CONTROLLER_TYPE "altera_generic_tristate_controller"

How I can set:

LAN_CONTROLLER_IRQ_INTERRUPT_CONTROLLER_ID 0
LAN_CONTROLLER_IRQ 2

?

in the QSYS program, the signals to the interrupt controller are connected and the interrupt is set to 2, but in system.h interrupt controller -1 and IRQ -1

how can I fix it?

UART is connected to IRQCONTROLLER also and it has parameters like this in system.h

#define LOG_UART_IRQ 0
#define LOG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0

The problem is altera_generic_tristate_controller only...



in the QSYS program, the signals to the controller are connected and the interrupt is set to 2
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EPCS4SI8N bonding diagram

June 19, 2018, 2:19 am
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Hi all,

I am searching for EPCS4SI8N bonding diagram( X-Ray), but so far i cannot find from website, any chance can provide from here?
thanks
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Compiling MMD library and AOCL utilities on Windows

June 19, 2018, 2:33 am
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We copy "a10_ref" to our base directory and want make binaries from sources for our MMD library and diagnose.exe / program.exe. Are many errors.
Questions:
1. Where search make.exe in Quartus 17.1 subdirectories ? Minimum 5 files is available.
2. Which version of Visual Studio (10, 12, 15, 17) may be used for using cl.exe and .h/.lib ?
3. Which version of MS Windows SDK (for search windows.h) is better ? In all our includes is duplicated macro "inline".
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Read and write from FPGA to DDR3

June 19, 2018, 8:12 am
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Hello,


first of all I'm a beginner to FPGA/SoC-development and I hope this kind of question hasn't been asked too often (i've used the search engine, but couldn't find a satisfying answer).
I'm currently working on a project involving a DE10 Nano development board with Cyclone V SoC (5CSEBA6U2317) and I'm trying to achieve the following:
I'm receiving data through the GPIOs of the board at a 1MhZ rate and need to store it on the DDR3 memory. After receiving and storing all data (around 150-200Mbyte) the data then needs to be buffered back into the FPGA in 40-Bit-Chunks for further processing.
So far I've figured out how to receive the Data and buffer it in a FIFO and also how to further process it, but i'm having trouble to understand how to achieve the above mentioned data storage.

Until now I've created an UniPHY IP-Core and tried to create a module in the Platform Designer of Quartus II, but without any success.


What would be the first steps to create such a DDR3-Controller? Are there any Step-by-Step Guides or tutorials that i could use? I would be very thankful for any directions an expert can give me.

Greetings OrangeClaw
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nStatus held low Cyclone IV EP4CE6E22

June 18, 2018, 1:24 am
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Hi,

I've designed a board with a Cyclone IV EP4CE6E22.
I have a problem with the config on the JTAG chain. My device is not detected.
I've checked all Vcc (I/O=3.3V, PLLA = 2.5V, VccINT= 1.2V) ;
nConfig is high but nStatus held low.
I have 10k pull-up (Vcc 3.3V) on this pin.

I don't understand what is my problem.

Please, help me.

Thanks
Alain
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avalon ST video protocol hard time

June 18, 2018, 1:59 am
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Hi everyone,
i'm working on arria10 soc board and i try to display a video that comes from a gigabit ethernet link and a 640x512 24b (8 bits per pixels + 3 color planes) rgb custom camera. For the moment, i don't use DDR4 for image buffering.
Instead i use a huge 2 ports on-chip memory for test (1310720 bytes). ( slave0 -> ram to dma interface(clock 148.5 MHz), slave1 -> camera rgb pixel (clock 125MHz))
I have a state machine that writes pixel data to this RAM on slave1 side while there is a DMA (university program one, consecutive addressing) that reads (slave0) this RAM
The vip mixer has 2 input : 1) 640*512 test pattern generator color bars 2) DMA

In my C program, i start IPs in this order 1)cvo 2)mixer 3)test pattern 4)dma
For the moment, i can display the color bars but as soon as i start the DMA, it disappears and only back ground from mixer is shown.

My questions are :
1- do i have to write a st control packet to ram firstor it's generated by dma itself?
2- if yes, is this control frame sequence valid?
sof + data_to_stvideo <= x"00000" & "1111"
data_to_stvideo <= x"00" & Iwidth(7 downto 4) & Iwidth(11 downto 8) & Iwidth(15 downto 12)
data_to_stvideo <= x"00" & Iheight(11 downto 8) & Iheight(15 downto 12) & Iwidth(3 downto 0)
data_to_stvideo <= x"00" & Interlacing_nibble & Iheight(3 downto 0) & Iheight(7 downto 4)
2- I write pixel data to ram like this but i'm not 100% sure : data_to_ram(31 downto 24) <= (others => '0') and data_to_ram(23 downto 0) <= red&green&blue and i increment address on next pixel

thank you for anything that can help me
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Timing issues between D5M camera module and PIOs buttons in NIOSII SBT

June 18, 2018, 2:31 am
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Hello everyone
I am of course no vice specially in timing the design. Kindly refer to the snapshot of my qsys system. This is in short a video capture system using D5M CMOS camera on DE-4 board. Video capture works pretty fine. The problem I face is in Software side and not in Hardware side. I mean in NIOS eclipse environment with C language, when I press pioButton have no effect i.e. code which is expected to run is not running. But when I press Hardware reset, very quickly after pressing reset the pioButton works fine. And as soon the video capture is started and getting displayed again on screen, the pioButton again goes like dead.

In simple words Video capture + display is working like mutually exclusive with pioButton. Either of these two may work. Once video capture is started PioButton have no effect.

All the connections are very well clear in snapshot. Other details:

DDR2 memory device speed grade is 533.333MHz; in general settings speed grade is 2; Memory clock frequency is 400MHz; PLL reference clock frequency is 50MHz; then you may see afi_clk is connected to all IPs except PIOs which are connected to 10MHz clock derived from pllInternal alt_pll IP.
Avalon MM-Clock crossing bridge master clock is connected to 10Mhz from alt_pll and slave clock with afi_clk of DDR.

My question is: Is there any necessary IP I must use to synchronize the events of PIOs and camera module (inculdes IPs Terasic_Camera, FrameBuffer, and Clocked Video Output)?
Or clocks distribution I am providing is wrong?

NOTE: C language code have no problem as I have tested the code running smoothly when after removing the Camera module which means disabling the camera and video capture gives no problem in Software at all.

Thanks a lot in advance. Snapshot is below:
Attached Images
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Error: L6366E: my_strcopy.o attributes are not compatible with the provided attribute

June 18, 2018, 5:08 am
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Hello,

I’m working on cyclone V based project using DS-5 AE tools.
I created a project using the Altera-Cyclone-V_RAM example of the DS-5 Examples & Programming Libraries’
The project compiles well and I can debug it without problem.
Then I created the assembler file according to the following example:
https://developer.arm.com/products/s...piler-features

This example is very simple and the file my_strcopy.s contains the following code:
PRESERVE8
AREA SCopy, CODE, READONLY
EXPORT my_strcopy ; Export symbol
my_strcopy ; R0 -> dest string
; R1 -> source string
LDRB R2, [R1],#1 ; Load byte + update addr
STRB R2, [R0],#1 ; Store byte + update addr
CMP R2, #0 ; Check for null
BNE my_strcopy ; Keep going if not
BX lr ; Return
END

When I compile the project I got the following error message:

armlink --cpu=Cortex-A9.no_neon.no_vfp --fpu=vfpv3 --scatter="../scatter.scat" --info=sizes -o"../Hello_and_ASM.axf" ./hello.o ./my_strcopy.o
Error: L6366E: my_strcopy.o attributes are not compatible with the provided attributes.
Object my_strcopy.o contains Build Attributes that are incompatible with the provided attributes.
Tag_THUMB_ISA_use = No Thumb instructions were permitted to be used (=0)
Tag_Advanced_SIMD_arch = Use of the Advanced SIMD Architecture (Neon) was permitted (=1)
Finished: 3 information, 0 warning and 1 error messages.


What can I do?
Thanks for your Help
Kind regards
Jerome
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Preloader Make untar failing.

June 18, 2018, 9:40 am
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I am attempting to compile a new preloader on windows using SOCEDS 18.0...but am failing at untar'ing the uboot-socfpga.tar.gz.


Chris@DESKTOP-NSSUV7O /cygdrive/f/VirtualBox VMs/share/rocketboards_image/17_1_DE10/DE0_NANO_SOC_18_0/software/spl_bsp
$ make
tar zxf /cygdrive/c/intelFPGA/18.0/embedded/host_tools/altera/preloader/uboot-socfpga.tar.gztar: Error opening archive: Failed to open '/cygdrive/c/intelFPGA/18.0/embedded/host_tools/altera/preloader/uboot-socfpga.tar.gz'
make: *** [uboot-socfpga/.untar] Error 1

Ideas?
Besides the point, I am trying to change the SOC Workshop Kernel Module #9 to use the FPGA 2 SDRAM instead of the FPGS 2 HPS (Heavyweight), by recompiling the preloader, as I've read this is why the FPGS 2 SDRAM is failing for me.

Right now I'm reinstalling SOCEDS into virtual machine, and trying again.
Project compiled with 18.0. SOCEDS is version 18.0


Thanks!
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Qsys Avalon MM Slave needs a slower clock. Best way to do this?

June 18, 2018, 11:41 am
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I’m modifying an existing Cyclone V Qsys design which is clocked from the HPS H2F user clock at 100 MHz . I need to add an Avalon Bus slave core to this system which requires a 50 MHz interface. It appears this will need it’s own 50 MHz clock reset, clock and Avalon MM bridge to interface to this my slave core. Is this correct or is there a better way to connect this?

Thank you for your attention
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Data Transfer from FPGA-to-HPS

June 18, 2018, 1:28 pm
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Hi Everyone,

To give some background here is what I am currently working on, what hardware I have, and what I am trying to implement to solve my issue.
Board: DE0-Nano-SOC 5CSEMA4U23C6

Issue: I will be receiving around data into the FPGA at 40MHz. I need to make this data available to the HPS. The data will be ready in around 37KB chunks, I am planning on using a double buffer system so say we need a 75KB space to store said data. My idea is that I will stream the data in, fill up the buffer, signal the HPS that it is ready, the HPS will read the data, package it, and send it over an Ethernet network. I have actually asked this question in another part of the forum here: https://alteraforum.com/forum/showth...654#post239654, but realized this section would be better suited to the question. Going off what was talked about there, I am trying to get the FPGA-HPS bridge working in order for the FPGA to write to the HPS's DDR3 RAM and then have the HPS read from it. I have set the board up from the QSYS side correctly I believe. I limited the HPS RAM for linux to 800 MB. Then I have been trying to write to address 0x32000000, with absolutely 0 luck in getting anywhere. I am not sure if I am setting up something wrong in Quartus, my C code, or some other issue. And would appreciate any assistance in this.
Thanks!
-Andrew

EDIT: Currently I am using Linux, but I would eventually like to move to BareMetal, for now though I am sticking with Linux.
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License File for Purchased IP

June 18, 2018, 1:55 pm
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Hi all,

Recently I purchased IPS-EMBEDDED from Mouser Electronics, which is supposedly the base IP suite (include ddr memory controller, 3-speed ethernet, etc.). Altera emailed me a product activation code and some vague instructions on how to obtain license files through Self Service Licensing centre.

The problem is that when I logged onto mySupport, the self service licensing page is empty (no products shown), and there is no way to specify the product I need to add. I also used the search button with the provided product activation code, but the system cannot process it.

I filed a service request 5 days ago, first they complained about me not using a work email. After updating my company information, I have not received any acknowledgement. I suspect that no one has looked at my service request yet.

The reason I post this question: I suppose there is something basic that I miss; the instructions on how to use a purchased IP should be intuitive or well-documented. I hope someone with experience dealing with Altera licenses can point me in the right direction.

Ben Chang
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New thread Lost

June 18, 2018, 2:13 pm
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Hi all,

I just posted a new thread titled "License File for Purchased IP" in the General discussion forum. After I hit submit new thread, the system brings me back to the forum listing, not the new post. I searched this title and found no matched result; looked at my posting history but again nothing. I tried to post the same thread with the same title, the system says this is a duplicate post and declines.

So where is this new post then? This is strange.

Ben
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Problem with Max 10 I've never seen before

June 18, 2018, 4:37 pm
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I have an issue with a MAX 10 design. I've never seen this problem before and I am baffled by it. I have down loaded the FPGA image, which includes a NIOS, and user application code to the internal flash memory. I generated a .hex file from the application code and created a combined .pof and programmed the CFM and UFM using the USB Blaster. After programming the device, I can verify the its programmed before and after cycling power. The application will execute after reset has negated while I have the board powered up on the bench. However, after installing the board in the system which it needs to function in. The system will come up and access the board to run its power-on tests. Somewhere in that time, the flash memory will be corrupted or altered in someway where is will not function. I can remove the board and return it to the bench and I can't verify either the CFM or UFM using the device programming tool. The device memory is not blank but it fails to verify. I can reprogram the device again but eventually, the device will suffer from the same problem again. When the board does retain it's configuration, it will function properly and the application runs without any exceptions and will continue to operate as long as it is powered up. This problem doesn't occur everytime and it is occurring on multiple boards of the same design. Any ideas, questions or suggestions? Thanks.
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How to design ALM for Aria 10?

June 18, 2018, 5:26 pm
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I have two simple 5-input and 3-input functions in Verilog.

Function 1: 3:1 Multiplexer
input a,b,c;
input [1:0] s1;
output wire east;


Function 2 : 2:1 Multiplexer
input d,e;
input s2; //sel line
output wire south;

Multiplexers are written with Case statements.
When I try so synthesize it in Altera with Aria - 10 FPGA selected. This gets mapped to 2-ALMs.

But I saw in datasheets that only 1-ALM is required to implement a 5-input and 3-input functions.
How do I force the ALM to map this logic in one Cell.
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Why address space bytes allocated by QSYS does not match the SPI IP core ?

June 18, 2018, 8:29 pm
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Hello everyone:
I have a question: Why QSYS automatically allocates address space bytes that do not match the number of internal register address space bytes defined by the SPI IP core?
Specific use is as follows:
I use SPI（3wire serial）IP in QSYS (Quartus II 11.1sp2) ,Parameter settings see Figure 1, after the completion of the set up, use "Assign Base Addresses " function,but the number of bytes that QSYS automatically allocates is only 8 bytes(see Figure 2), it not match the register map of SPI IP core define.(see Figure 3).
In addition,when the data width of the master port (Avalon MM) is 8 bits, no matter how the SPI sets the data bit width, the number of bytes that QSYS automatically allocates is 8 bytes.When the data width of the master port (Avalon MM) is 16 bits, no matter how the SPI sets the data bit width, the number of bytes that QSYS automatically allocates is 16 bytes,and so on.
My question is :
When the number of bytes that QSYS automatically allocates is 8 bytes,Which byte is the specific address of the "rxdata ",''txdata","status","control" and "slaveselect" register?
Looking forward to your answer, thank you very much!
Attached Images
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About path delay in my FPGA

June 18, 2018, 8:38 pm
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My dear,
My application is that a signal EN_in to my FPGA , and a EN_out from my FPGA to ADCs. Now I want to delay the signal for unknown ns to need the ADC timing,the detail ns is test by my teamer. So I set some deifferent paths and a probe IP in my design,so my teamer use the probe IP to select the best delay path to use.
--------------------------------------------------------------------------------
my design(.v):

input EN_in;
output EN_out;

(* keep *) wire EN_delay0;
(* keep *) wire EN_delay1;
(* keep *) wire EN_delay2;
(* keep *) wire EN_delay3;

assign EN_delay0 = EN_in;
assign EN_delay1 = EN_in;
assign EN_delay2 = EN_in;
assign EN_delay3 = EN_in;
assign EN_out = (probe==2'b00) ? EN_delay0 : ((probe==2'b01) ? EN_delay1 : ((probe==2'b10) ? EN_delay2 : EN_delay3));
--------------------------------------------------------------------------------
my constraint(.sdc):

set_min_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay0}] 1.000
set_max_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay0}] 2.000
set_min_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay1}] 3.000
set_max_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay1}] 4.000
set_min_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay2}] 5.000
set_max_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay2}] 6.000
set_min_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay3}] 7.000
set_max_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay3}] 8.000
--------------------------------------------------------------------------------

But,but...but...I found that 4 delay paths not work efficiently... There is just 570ns between The Max delay path and The Min delay path . And the min delay path isnot EN_delay3 .
My FPGA is EP4SGX230KH40. Help me.
Thanks all.
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QII 17.1 tristate controller IRQ -1 problem

June 19, 2018, 2:06 am
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Hello!

I use Quartus II 17.1 Standard edition with Stratix IV device. I have to connect LAN91C111 device. I use QSYS with altera_generic_tristate_controller for it.
After generation system.h file for embedded software development:

#define ALT_MODULE_CLASS_Lan_controller altera_generic_tristate_controller
#define LAN_CONTROLLER_BASE 0x10000
#define LAN_CONTROLLER_IRQ -1
#define LAN_CONTROLLER_IRQ_INTERRUPT_CONTROLLER_ID -1
#define LAN_CONTROLLER_IS_ETHERNET_MAC 1
#define LAN_CONTROLLER_LAN91C111_DATA_BUS_WIDTH 16
#define LAN_CONTROLLER_LAN91C111_REGISTERS_OFFSET 768
#define LAN_CONTROLLER_NAME "/dev/Lan_controller"
#define LAN_CONTROLLER_SPAN 65536
#define LAN_CONTROLLER_TYPE "altera_generic_tristate_controller"

How I can set:

LAN_CONTROLLER_IRQ_INTERRUPT_CONTROLLER_ID 0
LAN_CONTROLLER_IRQ 2

?

in the QSYS program, the signals to the interrupt controller are connected and the interrupt is set to 2, but in system.h interrupt controller -1 and IRQ -1

how can I fix it?

UART is connected to IRQCONTROLLER also and it has parameters like this in system.h

#define LOG_UART_IRQ 0
#define LOG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0

The problem is altera_generic_tristate_controller only...



in the QSYS program, the signals to the controller are connected and the interrupt is set to 2
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EPCS4SI8N bonding diagram

June 19, 2018, 2:19 am
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Hi all,

I am searching for EPCS4SI8N bonding diagram( X-Ray), but so far i cannot find from website, any chance can provide from here?
thanks
↧

Compiling MMD library and AOCL utilities on Windows

June 19, 2018, 2:33 am
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We copy "a10_ref" to our base directory and want make binaries from sources for our MMD library and diagnose.exe / program.exe. Are many errors.
Questions:
1. Where search make.exe in Quartus 17.1 subdirectories ? Minimum 5 files is available.
2. Which version of Visual Studio (10, 12, 15, 17) may be used for using cl.exe and .h/.lib ?
3. Which version of MS Windows SDK (for search windows.h) is better ? In all our includes is duplicated macro "inline".
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