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Read and write from FPGA to DDR3

June 19, 2018, 8:12 am
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Hello,


first of all I'm a beginner to FPGA/SoC-development and I hope this kind of question hasn't been asked too often (i've used the search engine, but couldn't find a satisfying answer).
I'm currently working on a project involving a DE10 Nano development board with Cyclone V SoC (5CSEBA6U2317) and I'm trying to achieve the following:
I'm receiving data through the GPIOs of the board at a 1MhZ rate and need to store it on the DDR3 memory. After receiving and storing all data (around 150-200Mbyte) the data then needs to be buffered back into the FPGA in 40-Bit-Chunks for further processing.
So far I've figured out how to receive the Data and buffer it in a FIFO and also how to further process it, but i'm having trouble to understand how to achieve the above mentioned data storage.

Until now I've created an UniPHY IP-Core and tried to create a module in the Platform Designer of Quartus II, but without any success.


What would be the first steps to create such a DDR3-Controller? Are there any Step-by-Step Guides or tutorials that i could use? I would be very thankful for any directions an expert can give me.

Greetings OrangeClaw
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Latency of the loop

June 19, 2018, 10:47 am
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Would the latency of the below loop be different for switch_loop = 0 and switch_loop =1? The html report generated for the below kernel includes the latency of the global and local memory access.

Eg: If global memory access takes 5 cycles then the start cycle of local memory access is 6 and hence the start cycle of additon operation is 9 (3cycles of local memory access). Doesnt the latency of the loop depend on the if condition based on kernel argument by host?

__kernel
__attribute__((task))
void dummy_kernel
(
__global *restrict bottom ,
__local *restrict top,
__global *restrict final,
uchar switch_loop)

{

float private;

for (unsigned i = 0; i< 20; i++) {

if (switch_loop == 0)
private = global_memory[i];
else
private = local_memory[i];

private = private + 1;
final[i] = private;
}
}
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How to use anything other than the dedicated refclk with Stratic GX Transceiver

June 19, 2018, 11:30 am
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Hello,

I've been working on a design on the Stratix V GX SI Development Board. On this board, there exists a 644MHz refclock on the refclock input for the bank that I wish to use. I need to feed a different refclock to it, but have been utterly unable to get any alternate design to pass the Quartus fitter, even though according to documentation it should be possible to do so. I can't find any design examples on how to get this to work.

I've tried using a fractional PLL output, and I've tried using the ALTCLKCTRL component.

What am I missing?

Thanks in advance,
Ray
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No Rule To Make Target: socfpga_cyclone5_config

June 19, 2018, 11:36 am
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Hi everyone,

I have a Cyclone V FPGA, using Quartus Lite 18.0, and EDS 18.0.0.614. When trying to make the preloader, after generating the BSP, I get the error:
Code:
‘generated/build.h’ -> ‘uboot-socfpga/board/altera/socfpga/build.h’‘generated/iocsr_config_cyclone5.c’ -> ‘uboot-socfpga/board/altera/socfpga/iocsr_config_cyclone5.c’
‘generated/iocsr_config_cyclone5.h’ -> ‘uboot-socfpga/board/altera/socfpga/iocsr_config_cyclone5.h’
‘generated/reset_config.h’ -> ‘uboot-socfpga/board/altera/socfpga/reset_config.h’
‘generated/pll_config.h’ -> ‘uboot-socfpga/board/altera/socfpga/pll_config.h’
‘generated/pinmux_config_cyclone5.c’ -> ‘uboot-socfpga/board/altera/socfpga/pinmux_config_cyclone5.c’
‘generated/pinmux_config.h’ -> ‘uboot-socfpga/board/altera/socfpga/pinmux_config.h’
‘generated/sdram/sdram_config.h’ -> ‘uboot-socfpga/board/altera/socfpga/sdram/sdram_config.h’
C:/intelFPGA/18.0/embedded/host_tools/cygwin/bin/make CROSS_COMPILE=arm-altera-eabi- MAKE=/bin/make CYGPATH=C:/intelFPGA/18.0/embedded/host_tools/cygwin/bin/cygpath HOSTCC=x86_64-w64-mingw32-gcc HOSTSTRIP=x86_64-w64-mingw32-strip -C uboot-socfpga socfpga_cyclone5_config
make[1]: Entering directory '/cygdrive/c/Users/ashivers/Documents/SPQ-X/SPQ_X_Project/QuartusCode/soc_system_160807_restored/software/spl_bsp/uboot-socfpga'
make[1]: *** No rule to make target 'socfpga_cyclone5_config'.  Stop.
make[1]: Leaving directory '/cygdrive/c/Users/ashivers/Documents/SPQ-X/SPQ_X_Project/QuartusCode/soc_system_160807_restored/software/spl_bsp/uboot-socfpga'
make: *** [uboot-socfpga/.config] Error 2
Which is strange since not 5 minutes before hand I was able to successfully run that command before I realized I did not enable FAT in the BSP editor. But now it won't work whether or not FAT is selected. I've tried restarting, regenerating the BSP, recompiling Quartus project, then regenerating, no dice. Was wondering if anyone had any advice?
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How to config Arria 10 10GBase-R support SFP+ optic module

June 19, 2018, 6:21 pm
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Hi,everyone!
I'm using the "Arria 10 1G/10GbE and 10GBASE-KR PHY" for a design I'm working on with the Arria 10,and fpga serdes connect to SFP+ optic module.
Described in the manual support edc,on page 6 "Electronic Dispersion Compensation (EDC) support for XFP, SFP+, QSFP, and CFP optical
module",but intel did not explain how to use this function？？？
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How to make communication between computer and Quartus using Python?

June 19, 2018, 11:17 pm
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Hi,

I am very new to this tool Altera Quartus, but i need to build the design that i need to give command from the coumputer to PC through Python. So, my question is how to build the design in Altera Quartus.

If any example design, please share me. It will be helpful for me or please guide me to build this design.
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limit the linux partition in DDR3 memory of DE1-SOC board

June 20, 2018, 1:25 am
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how can i devide the ddr3 memory between the linux and FPGA in DE1 soc board
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memtool linux command

June 20, 2018, 2:07 am
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Hi
Im using the DE1 soc board , and i want to transfer data from FPGA to HPS ddr3 memory and to do that i need to take the FPGA SDRAM port out of reset using command "memtool" : memtool -32 0xFFC25080=0x110
https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Writing_to_HPS_Memory

but the command returns in the putty terminal command not found

I need your help
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sdo file not generated in altera

June 20, 2018, 3:46 am
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Maximum inputs per LAB

June 20, 2018, 4:18 am
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Can't find this documented anywhere. Is there a cap on the total number of signals that can be routed into a single LAB? Take Cyclone V, to be specific.

From the datasheets, I was under the impression that the only limit is on signals per ALM - 8 lines not counting clock, carry, etc, which would allow me to pack incoming 80 wires per LAB. But I've been trying to work out the root cause of routing difficulties in my design, started manually assigning logic to locations, and got a curious error message:

"Info (170015): LAB legality constraint that was not satisfied: LAB requires more input signals requiring LAB lines than are available. Resources used: 65. Resources available: 46."
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Getting CL_OUT_OF_RESOURCES with clenqueuewritebuffer API

June 20, 2018, 6:47 am
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Hi,
I am transferring one 4k frame(3840x2160) from Host to device. My device global memory is 2GB.
We are creating memory object of size 3968 * 2272. If I am using clcreatebuffer, with CL_MEM_READ_ONLY | CL_MEM_COPY_HOST_PTR flags, its running for all 600 iterations.
dstPtr1 = clCreateBuffer(context, CL_MEM_READ_ONLY | CL_MEM_COPY_HOST_PTR, 3968 * 2272, hostPtr1, &err);
if ((CL_SUCCESS != err) || (NULL == dstPtr1)) {
printf("Error in clCreateBuffer dstPtr1 %d\n", err);
exit(-1);
}


If we are using below, then it's throwing CL_OUT_OF_RESOURCES after 230 iterations even if we release the memory.
dstPtr1 = clCreateBuffer(context, CL_MEM_READ_ONLY, 3968 * 2272, NULL, &err);
if ((CL_SUCCESS != err) || (NULL == dstPtr1)) {
printf("Error in clCreateBuffer dstPtr1 %d\n", err);
exit(-1);
}
err = clEnqueueWriteBuffer(commandQueue[0], dstPtr1, CL_TRUE, 0, 3968 * 2272 * sizeof(pixel), hostPtr1, 0, NULL, NULL);
if (CL_SUCCESS != err) {
printf("Error in clEnqueueWriteBuffer dstPtr1 %d\n", err);
exit(-1);
}
What I am not able to understand is both the API calls does the same operation of copying the data from Host to device, but only when I use clEnqueueWriteBuffer I am getting CL_OUT_OF_RESOURCES. Is there any difference between them.


Thanks in advance.
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Cyclone V MT25Q256 write from NIOS software

June 20, 2018, 7:37 am
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Hi.

We are evaluating alternative FLASHs for the Altera EPCQ256 chip. The recommended MT25Q256 is working with our design regarding programming, booting and remote update. But I cannot write data from my NIOS II firmware.

My setup: Quartus Prime Lite 18.0, with the quartus.ini file described in https://www.altera.com/support/suppo...--256mb--.html

In QSYS, I used to have the Serial Flash Controller Intel Altera IP, and I use the HAL commands from sys/alt_flash_dev.h. When trying to write the return value is 0 (OK), but the data is not present when reading back.

So I tried the Serial Flash Controller Intel Altera IP II with the same settings, but still not working. The Generic Quad SPI controller II lets me select the MT25Q512 (not exactly the type we use), but wants me to export the conduit pins. But the programming pins are dedicated, and I cannot connect to them.

Any hints?

Thanks for reading,
Heiko
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Arria 10 GX Dev Kit PCie DMA Timeout on a NUMA HPC

June 20, 2018, 8:22 am
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Hello, everyone

I am currently working with FPGA-based acceleration for an HPC cluster, and I am having trouble to communicate with my FPGA boards using DMA on a NUMA environment.

My Host topology is as follows:

(UPI)
DDR0 <----> CPU0 <---------------> CPU1 <---> DDR1
|
|
Arria 10 GX <----------> Arria 10 GX
Dev Kit A (PCIe) Dev Kit B

I have two Arria 10 GX Dev Kits Endpoints attached to the first CPU, which works as a PCI Root Complex. I am also using an adaptation of the "altera_dma" driver to send and receive data to and from the FPGAs. Inside the boards I have simply programmed the "PCIe DMA with external memory" reference design with no extra circuit. The design was synthesized using both Quartus 17.0 and Quartus 18.0, with the same results. The two CPUs are identical (Xeon 6148) with integrated PCIe controllers.

With this configuration, from the Host I am able to read and write any Avalon MM address (through PCIe BAR[4]+offset) using io[write/read] system calls. However, I can't get the DMA controller to transfer any data. Every DMA transaction ends up with a DMA Timeout.

Some extra information:

- The same driver and reference design works perfectly on my workstation, which has a single CPU and FPGA board;
- The same problem occurs when I use only one FPGA on the HPC Host;
- Both devices are correctly identified by the driver probe function, and a corresponding "/dev/devicenode" is created for each FPGA.

The configuration that works:
(PCIe)
DDR <----> CPU <----> Arria 10 GX Dev Kit


I believe that the problem might be related to PCI memory allocation on a NUMA environment, hence it is the only different thing from my workstation.

Have you guys experienced any similar problems or are aware of any limitations of the Arria 10 PCIe DMA Hard IP used in the reference design regarding this type of environment?
If so, could share some information to help me out?

Thanks a lot, you guys!

Regards
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System Verilog Pin Assignment Issues

June 20, 2018, 9:43 am
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Newbie question - Just bought my first FPGA and working through examples to understand design and coding. My first example using a block diagram and .v file worked fine. My next try was using a book that has System Verilog examples. When entering System Verilog coding and going to Pin Planner in Quartus Prime 18 (Lite Edition), the pin definitions are not the same and not correct. Any idea what I am doing wrong? Same device number was used.
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Getting the PRE_FLOW_SCRIPT_FILE thing to work

June 20, 2018, 9:52 am
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Folks,
I have been trying to get a tcl script to run before compile to no avail. I have a tcl script to create a vhd file with the build date and time in it, gleaned from the examples on the net. I can run this script from the tcl cmd line in qts (15.1). The tcl file runs and creates the correct vhd file contents. I put this in the projects qsf file:

set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:build_date.tcl"

build_date.tcl resides in the projects root dir, ext to the .qsf file
When I initiate a build, I dont see it running
I tried entering this command manually at the tcl command line in qts as well - still does not get run.

Questions:
Where is the build_date.tcl file supposed to be placed?
when does the .qsf file get read?
How do I debug this?

Thanks,
Ed
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What are these different arch types in FPGA binaries release folder in OpenVino

June 20, 2018, 9:54 am
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i understand 0.8.1 is the DLA version, 16x32 is k vectorization and channel depth and fp16 is the floating point precision. but what does arch13/09/06 mean ?
0-8-1_a10dk_fp11_16x32_arch16.aocx 0-8-1_a10dk_fp16_8x24_arch13.aocx 0-8-1_a10dk_fp16_8x48_arch06.aocx
0-8-1_a10dk_fp11_16x32_arch19.aocx 0-8-1_a10dk_fp16_8x32_arch09.aocx 0-8-1_a10dk_fp16_8x48_arch08.aocx
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HMC pins in the CycloneV

June 20, 2018, 11:06 am
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Hello.
I plan to use 5CSEMA5 with hard memory controller and single SOC core. HMC in the FPGA part of 5CSEMA5 has got a lot of pins for DDR3 connection.
I want to use only part of special HMC pins for connection to DDR3.
Can I use free pins of HMC (for example DQ[16 - 39]) as IO and use their for other signals?

Thanks.
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Configuring Arria V using MAX II and flash

June 20, 2018, 12:10 pm
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Hi everyone,
I am trying to configure Arria V using Max ii CPLD and on board flash using PFL IP.
My question is
1) when I try to generate the pof file for the CPLD, it asks me for the configuring device, but I cannot find the configuring device as EPM1270 in the drop down list.
How do I get around this?
2) AN478 says, instantiate the PFL megafunction and make pin assignments. What am I supposed to do in this?

Thank you in advance.
RSK007
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Source Synchronous interface with Cyclone 10 GX Transceivers

June 20, 2018, 12:49 pm
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Hi,

My end goal is to implement Source Synchronous interface with Cyclone 10 GX Transceivers. For transmit, can I use one transceiver as a clk line and drive 4 other transceiver as data line by controlling the phase of 4 data lines wit the clock line?
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What can I do for 'Main Optimizer failed' error in Intel HLS?

June 20, 2018, 7:18 pm
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Hi,

My component has two stream in inputs and one stream out output.
The two inputs pass through the Shift register and perform multiply operations between the elements.
x86 execution is not a problem. An error such as the following occurs when executing build.bat test-fpga.

"Instruction does not dominae all users!"

One stream in is a blocking read, and the other stream in is a non-blocking read.
Changing both data to non-blocking causes the same error.

Shift register has no errors, and errors occur when multiplying the elements.
The data type is ac Brother fixed, and is an operation of 8bit and 1bit.

I uses Quartus 17.1 version. What can I do?
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