MAX 10 LVDS serdes CDR

June 20, 2018, 8:03 pm

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Hello,


This is Doosoo Ha, senior engineer of Opticis.

I am designing a LVDS serdes system using two(2) of MAX 10 devices.

I plan to build LVDS serdes system as transmitting data with only one LVDS signal line.

The LVDS using in my system is "LVDS with embedded clock". In other words, a separate clock signal for LVDS deserialization is not transmitted. I set LVDS serialize as factor is ‘10’ and the data rate as ‘100Mbps’.

I confirmed LVDS output is normal when inputting K28.5 data to LVDS serialize block.

After that, I designed deserialize block to LVDS deserialize block but problem has occurred during its verification.

What it saying as a problem is that the clock was asynchronized during deserialization because it was designed with "without clock signal".
I would like to know if there is any way clock not being asynchronized when I use LVDS with embedded clock without transmitting a separate clock signal for LVDS deserialization.

Please assist me how I can solve this problem.

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How used MAX10 LVDS Serdes CDR

June 20, 2018, 8:04 pm

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Hello,
This is Doosoo Ha, senior engineer of Opticis.

I am designing a LVDS serdes system using two(2) of MAX 10 devices.

I plan to build LVDS serdes system as transmitting data with only one LVDS signal line.

The LVDS using in my system is "LVDS with embedded clock". In other words, a separate clock signal for LVDS deserialization is not transmitted. I set LVDS serialize as factor is ‘10’ and the data rate as ‘100Mbps’.

I confirmed LVDS output is normal when inputting K28.5 data to LVDS serialize block.


After that, I designed deserialize block to LVDS deserialize block but problem has occurred during its verification.


What it saying as a problem is that the clock was asynchronized during deserialization because it was designed with "without clock signal".
I would like to know if there is any way clock not being asynchronized when I use LVDS with embedded clock without transmitting a separate clock signal for LVDS deserialization.

Please assist me how I can solve this problem.

Choosing right flash size for storing cylcone V configuration file

June 20, 2018, 11:21 am

≫ Next: Nallatech 385A Quartus Fitter Failed

≪ Previous: How used MAX10 LVDS Serdes CDR

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Hello all,

I am new to FPGA development.
I want to know some basic info regarding flash memory.
On what basis can I choose the size of a flash memory.
My sof file is of 7MB and pof which i generated is of 16MB size.The rbf which i generated is of 32MB.
I am not sue whether i did something wrong or not.
Is it possible to choose a 16MB flash and which i assume that i need to refer the size of pof file.
How to set the option bit .What address i need to put it for option bit?
is it possible to store more than 1 fpga images in the 16MB flash in different pages?
please give me your valuable answers
thanks

Nallatech 385A Quartus Fitter Failed

June 20, 2018, 1:45 pm

≫ Next: Reg., DPCLK pins in MAX 10 FPGA

≪ Previous: Choosing right flash size for storing cylcone V configuration file

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I could use some help compiling a fairly simple, Intel authored OpenCL kernel on a Nallatech 385A (GX1150). After about four hours after running the following command (or with the default board p385a_sch_ax115 and various other attempts)

Code:

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aoc -v -report sha1.cl -DALTERA_CL -DFPGA -board=p385a_min_ax115

---

we get the following output:

Code:

---

aoc: Environment checks are completed successfully.
aoc: If necessary for the compile, your BAK files will be cached here: /var/tmp/aocl/gm78
You are now compiling the full flow!!
aoc: Selected target board p385a_min_ax115
aoc: Running OpenCL parser....
aoc: OpenCL parser completed successfully.
aoc: Optimizing and doing static analysis of code...
aoc: Linking with IP library ...
Checking if memory usage is larger than 100%


!===========================================================================
! The report below may be inaccurate. A more comprehensive         
! resource usage report can be found at sha1/reports/report.html   
!===========================================================================


+--------------------------------------------------------------------+
; Estimated Resource Usage Summary                                  ;
+----------------------------------------+---------------------------+
; Resource                              + Usage                    ;
+----------------------------------------+---------------------------+
; Logic utilization                      ;  108%                    ;
; ALUTs                                  ;  79%                    ;
; Dedicated logic registers              ;  37%                    ;
; Memory blocks                          ;  42%                    ;
; DSP blocks                            ;    0%                    ;
+----------------------------------------+---------------------------;
aoc: First stage compilation completed successfully.
Compiling for FPGA. This process may take a long time, please be patient.
Error: Quartus Fitter has failed! Breaking execution...
Error: Compiler Error, not able to generate hardware

---

The end of quartus_sh_compile.log shows:

Code:

---

Info: Command: quartus_cdb -t import_compile.tcl
Info: Using INI file /home/gm78/intel/sha1_export_4_11_2018/device/sha1/quartus.ini
Info: Checking for OpenCL SDK installation, environment should have INTELFPGAOCLSDKROOT defined
Info: INTELFPGAOCLSDKROOT=/home/gm78/intelFPGA_pro/17.1/hld
Info: Successfully completed BAK flow
Info: To reduce compile time on future compiles, you can generate a BAK cache by adding the arguments '--bsp-flow regenerate_cache' to aoc to skip BAK
Info: Retry strategy set to "retry-flat"
Info: Initial preservation set to "final"
Info (125061): Changed top-level design entity name to "top"
Info (125061): Changed top-level design entity name to "kernel_system"
Info (16677): Loading synthesized database
Info (16734): Loading "synthesized" snapshot for partition "root_partition".
Info (16678): Successfully loaded synthesized database: elapsed time is 00:00:22
Info: Performing a fit attempt
Error: Quartus Fitter has failed! Breaking execution...

---

Not sure which log(s) are relevant to tracking down the problem. Please let me know and I can post the additional information.

Many thanks.

Reg., DPCLK pins in MAX 10 FPGA

June 21, 2018, 1:48 am

≫ Next: PCIE legacy interrupt

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Dear sir,

Can I use DPCLK pin as user output pin in MAX 10 FPGA.
We are using 10M08DCU324 FPGA in our design

Kindly respond to this mail.


Regards,
Thulasi

PCIE legacy interrupt

June 21, 2018, 2:09 am

≫ Next: Unable to Flash EPCQ32A via SFL IP

≪ Previous: Reg., DPCLK pins in MAX 10 FPGA

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Dear all：

I was use IP Complier for PCIE to realize pcie interface,Completer only,single DW completer,endpoints mode,without CRA, generated by qsys.

Now, i want to use legacy interrupt, base on the handbook:

1、After power up, the IP core starts in INTX mode
2、In legacy mode,The app_int_sts input port controls interrupt generation.
3、In my qsys ，PCIe interrupt enable register bit was assigned to 0x0000ffff

But i can't find the app_int_sts in qsys,and in this file"pcie_hard_ip_0" app_int_sts was assigned to 0.
So,how can i use legacy interrupt with completer only,single DW mode ?
Which signal can be export to top level to assert interrupt?
please give me some suggestion ,thanks very much!
software version :13.1

youming

Unable to Flash EPCQ32A via SFL IP

June 21, 2018, 2:28 am

≫ Next: Arria 10 GX OpenCL setup question

≪ Previous: PCIE legacy interrupt

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Hallo,

we have a nasty problem with our new design. I tried it with several boards and the schematic is checked. The hardware seems fine.
We use a Cyclon V 5CEBA4U19 device with a attached EPCQ32A Flash.

When we programm the config directly via the .sof to the FPGA it works fine. This means the progress is 100% and Quartus
says "Programmer operation was successfull"

If I generate a .jic File to flash the EPCQ32A it fails. Progress stops at 89% and the error message is
"Flash Loader IP not loaded on device 1" (see attached Images)
It seems that already the SFL cannot programmed.


Info (209060): Started Programmer operation at Thu Jun 21 11:17:09 2018
Info (209016): Configuring device index 1
Info (209017): Device 1 contains JTAG ID code 0x02B050DD
Info (209007): Configuration succeeded -- 1 device(s) configured
Error (209062): Flash Loader IP not loaded on device 1
Error (209012): Operation failed
Info (209061): Ended Programmer operation at Thu Jun 21 11:17:15 2018



We tried 1000 of different options and videos and instructions, but nothing helps.

- Windows 10 / Windows 7
- Quartus Prime Lite Edition 18.0 (also tried with 17.1)
- JTAG via USB Blaster
- Cyclon V 5CEBA4U19
- EPCQ32A
- connected Signals EPCQ32A to the FPGA: D0-D4; DCLK; nCSO

Can someone help?

Marcus

Attached Images

• Image.JPG (84.5 KB)
• Image2.JPG (34.4 KB)

Arria 10 GX OpenCL setup question

June 21, 2018, 7:03 am

≫ Next: EMIF example design calibration fail on Stratix10

≪ Previous: Unable to Flash EPCQ32A via SFL IP

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I have an Arria 10 GX development kit that I am trying to set up for OpenCL. Thus far I have been able to program the board with the initial configuration for the MAX V and the Arria 10, but I have been unable to flash the boardtest design to the board with aocl flash. It outputs the help text for aocl flash even though the arguments are correct, and occasionally it will show that a syntax error occurred in a script that it runs, like this:

Code:

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sh: 1: Syntax error: "(" unexpected

---

I have been following this guide and running the command as described:

Code:

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aocl flash acl0 boardtest.aocx

---

Has anyone else experienced this? I have also been able to compile the driver with no problem but I cannot use it without a default configuration flashed to the board.

Thanks in advance for your help!

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EMIF example design calibration fail on Stratix10

June 21, 2018, 7:33 am

≫ Next: Using Timequest to Analyze Processor Bus Interface

≪ Previous: Arria 10 GX OpenCL setup question

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Hi guys,

I'm testing EMIF on Statix 10 DevKit with RLDRAM3 and I'm running into some issues that have been blocking me for more then a week.
Here is what I did:
I chose a preset "RLDRAM3 MT44K16M36-093E" based on this documentation (related to Arria10) :
https://www.altera.com/documentation...a1439506702904
Then I generated the example design.
After programming the S10 dev kit FPGA, I got the following signals status from the ISSP gui :

emif_s10_0_status_local_cal_fail = 1
emif_s10_0_status_local_cal_success =0
emif_s10_0_tg_0_traffic_gen_fail = 1
emif_s10_0_tg_0_traffic_gen_pass = 0
emif_s10_0_tg_0_traffic_gen_timeout = 1

From what I understood the design didn't even pass the calibration phase.
I have been reading many documents about S10 EMIF, however none of them helped me to get over this issue.
How can I be sure that I'm using the correct preset. any document on that would be a great help?

which parameters could cause this problem ?
where can i find the presets of the HILO memory Daughtercards ?
I have to mention that I left the pin assignment for quartus to handle. Fitter auto pin assignment is aligned with the pin assignment of the EMIF example that came within the S10 dev kit package.

Using Timequest to Analyze Processor Bus Interface

June 21, 2018, 11:20 am

≫ Next: Altera Avalon I2C Master Core API Timeout

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We have a design with a processor connected to the FPGA using standard address, data and control signals. This processor uses an internal clock of 200 MHz to control these signals and we have a 200 MHz clock inside the FPGA. However, we do not have physical access to the internal processor clock so we have no direct timing relationship between the two clocks. Because Timequest requires clock relationships to analyze timing, what is the correct method to implement the design and analyze timing?

It would seem that because we don’t know relationship between the internal processor clock and the FPGA clock we have a problem establishing IO delays and other timing relationships with the processor. Do all the signals need to be treated as asynchronous and suffer the penalty of a 2-clock synchronizer?

We have read a number or forum entries that have some relation to this subject. We also followed the Rysc “Timequest User Guide” which is very good but doesn’t seem to cover this situation. It seems like this would be a common problem but I have not seen examples on the topic. Any advice or ideas that might address this situation would be greatly appreciated.

Altera Avalon I2C Master Core API Timeout

June 21, 2018, 11:34 am

≫ Next: SPI core as Master mode?

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I am using the API with the Altera Avalon I2C Master core in non-interrupt mode. It works fine except when I try to access a device that is not currently on the I2C bus. Even though the driver code appears to have timeouts coded, it takes over an hour to timeout with a 100 MHz NIOS processor. Has anyone found and solved this problem?

Thanks,
Ron

SPI core as Master mode?

June 21, 2018, 1:01 pm

≫ Next: Build HPS Hardware

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Hi. Still getting the ropes here. I'm including SPI peripherals to my design for Max10 FPGA. Is it possible instantiate an SPI core in Platform Designer as master?, using Max10 FPGA?, Quartus Prime 17.1 Lite?, Platform Designer?
I seem to be coming up empty handed, but may not be using the right search terms. To know i'm on the right track or not, i'd just like to know from someone if what i am looking for exists. Thanks so much.

Build HPS Hardware

June 21, 2018, 1:28 pm

≫ Next: Error in library module cyclonev_atoms_ncrypt

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Hello, I have been searching for a guide that shows how to build the hardware for the HPS in Quartus. It would appear I use platform designer and create the necessary hdl from there, then add the .qip file to my project and set it as Top of Hierarchy. I have tried that and am getting these errors during place and route.

Error (174068): Output buffer atom "hps_hps_0:hps_0|hps_hps_0_hps_io:hps_io|hps_hps_0 _hps_io_border:border|hps_sdram:hps_sdram_inst|hps _sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy| hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p 0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_ cyclonev:altdq_dqs2_inst|extra_output_pad_gen[0].obuf_1" has port "SERIESTERMINATIONCONTROL[0]" connected, but does not use calibrated on-chip termination


I have provided my Platform Designer design in an image.


Is there a guide for how to do this? Also, are there any special connections that need to be made in platform designer so I can open a terminal and interact with the Linux shell once I have built and booted the software? It seems every guide I check just talks about the hardware/software handoff and other software Linux tools that Altera offers, but I cannot find anywhere that demonstrates the basics of setting up the ARM in the hardware design.

Xilinx has tons of User Guides for their Zynq PS and PetaLinux tools, so surely Altera must have them somewhere.

Attached Images

• hps_attempt.jpg (20.0 KB)

Error in library module cyclonev_atoms_ncrypt

June 21, 2018, 2:44 pm

≫ Next: kernel driver mismatch after switching from SDK 16.1 to 17.1

≪ Previous: Build HPS Hardware

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I am attempting to run a simulation with design components from QSYS.

I am running the msim_setup.tcl script provided by QSYS and am getting the following error message...

# vsim -t ps -L work -L work_lib -L error_adapter_0 -L altera_epcq_controller_core -L altera_asmi_parallel -L rsp_mux -L cmd_mux -L cmd_demux -L router_001 -L router -L avalon_st_adapter -L crosser -L rsp_mux_002 -L rsp_mux_001 -L rsp_demux_011 -L rsp_demux_009 -L rsp_demux_005 -L rsp_demux_004 -L rsp_demux_002 -L rsp_demux -L cmd_mux_002 -L cmd_demux_002 -L cmd_demux_001 -L epcq_controller_0_avl_mem_burst_adapter -L nios2_qsys_data_master_limiter -L router_014 -L router_007 -L router_005 -L router_003 -L router_002 -L avalon_internal_bram_interface_avalon_slave_agent -L nios2_qsys_data_master_agent -L avalon_internal_bram_interface_avalon_slave_transl ator -L nios2_qsys_data_master_translator -L remote_update_controller -L remote_update_core -L cpu -L dll0 -L oct0 -L c0 -L s0 -L p0 -L pll0 -L p2b_adapter -L b2p_adapter -L transacto -L p2b -L b2p -L fifo -L timing_adt -L jtag_phy_embedded_in_jtag_master -L rst_controller -L irq_synchronizer -L irq_mapper -L mm_interconnect_1 -L mm_interconnect_0 -L sysid_qsys -L sysclk_timer -L remote_update_0 -L onchip_mem -L nios2_qsys -L mem_if_lpddr2_emif -L mddr_to_mm_bridge_0 -L jtag_to_avalon_master -L hw_git_hash -L ext_int -L epcq_controller_0 -L avalon_internal_bram_interface -L avalon_external_interface_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver C5G_QSYS

# Start time: 15:55:58 on Jun 21,2018

# ** Note: (vsim-3812) Design is being optimized...

# ** Error: C:/bin/altera/17.0.1/quartus/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v(38): in protected region

Anyone have an idea on what is causing this?

Thanks!
Mike

kernel driver mismatch after switching from SDK 16.1 to 17.1

June 21, 2018, 8:29 pm

≫ Next: Use Cyclone 10 LP to replace LVDS transceiver

≪ Previous: Error in library module cyclonev_atoms_ncrypt

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We have recently switched from SDK16.1 to 17.1

The aocl diagnose works fine.
The aoc -list-boards shows the boards as expected.
The aoc full compile works.
The make works for the host program.

But, when trying to run the hello_world demo the following errors occur. Same for the vector_add demo.

It seems that the Nallatech board driver has been updated to 17.1 (as expected) but the host program
is still somehow using 16.1.

How is this happening? How to fix?


bin/host from hello_world produces:

MMD ERROR: Kernel driver mismatch: The board kernel driver version is nalla_pcie.17.1.4301bd558eaba33392adec0078bd82d8, but
this host program expects nalla_pcie.16.1.1.d41d8cd98f00b204e9800998ecf8427e .
Please reinstall the driver using aocl install.

MMD ERROR: Kernel driver mismatch: The board kernel driver version is nalla_pcie.17.1.4301bd558eaba33392adec0078bd82d8, but
this host program expects nalla_pcie.16.1.1.d41d8cd98f00b204e9800998ecf8427e .
Please reinstall the driver using aocl install.
Querying platform for info:
==========================
CL_PLATFORM_NAME = Intel(R) FPGA SDK for OpenCL(TM)
CL_PLATFORM_VENDOR = Intel(R) Corporation
CL_PLATFORM_VERSION = OpenCL 1.0 Intel(R) FPGA SDK for OpenCL(TM), Version 17.1

ERROR: CL_DEVICE_NOT_FOUND
Location: ../common/src/AOCLUtils/opencl.cpp:356
Query for number of devices failed

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Use Cyclone 10 LP to replace LVDS transceiver

June 22, 2018, 1:38 am

≫ Next: FPU hardware not being used by Newlib

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In my design, I am using Cyclone 10 LP. And I am using a LVDS transceiver SN65LVDT14QPWREP to communicate with another PCB. It works fine.
To lower the system cost, I am considering to integrate the LVDS transceiver into Cyclone 10 LP, then SN65LVDT14QPWREP can be saved.
As the FPGA supports true LVDS pins, I believe this idea works.

I am a new guy using FPGA, anybody can suggest?

FPU hardware not being used by Newlib

June 22, 2018, 4:25 am

≫ Next: EMIF on Stratix 10 Dev Kit miss board file

≪ Previous: Use Cyclone 10 LP to replace LVDS transceiver

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I am trying to build some code that uses plenty of math operations like powf, expf, logf, etc.
I know that these are first translated into Newlib implementations which, in turn, should be using the underlying FPH2 that I have instantiated with a NiosII CPU.

I see the custom instruction compile flags being used when I rebuild Newlib, but the code is way slower than I anticipated, and the disassembled code for the __ieee754_powf (as an example), contains many calls to soft-implemented floating point multiplications (__mulsf3), additions (__addsf3), subtractions (__subsf3), and divisions (__divsf3), as opposed to using the corresponding FPH2 custom instructions.

While these simple operations are inferred in my own C code, then are not being propagated into the Newlib routines.
So, if I use a floating point multiplication in my code, it uses the FPH2.
If I use a powf (which translates to a Newlib soft implementation), it does not make use of the FPH2.

What could I be missing here?


Here is the command line that Eclipse executes for generating the Newlib:

nios2-newlib-gen --no-multilib ./newlib-build-tmp ./newlib --custom " -O2 -g -Wall -mno-hw-div -mhw-mul -mno-hw-mulx -pg -fno-math-errno -mcustom-fabss=224 -mcustom-fadds=253 -mcustom-fcmpeqs=227 -mcustom-fcmpges=228 -mcustom-fcmpgts=229 -mcustom-fcmples=230 -mcustom-fcmplts=231 -mcustom-fcmpnes=226 -mcustom-fdivs=255 -mcustom-fixsi=249 -mcustom-floatis=250 -mcustom-fmuls=252 -mcustom-fnegs=225 -mcustom-fsubs=254 "

EMIF on Stratix 10 Dev Kit miss board file

June 22, 2018, 5:25 am

≫ Next: Which FPGA/CPLD dev-kit should I go for ?

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Hi all

i'm working on EMIF for stratix 10 Dev KIT
while generating the IP i can't find my board listed in the presets
how can i add it ?
if i can't what should i do ?

Thanks

Which FPGA/CPLD dev-kit should I go for ?

June 22, 2018, 6:15 am

≫ Next: EMIF Toolkit create Memory Interface Connection problem

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I want to learn more about Avalon interfaces, Quartus Platform Designer, NIOS II, etc.
I know people may have preferences, but for learning more about digital design, which board should I go for ?
Which board will have more reference designs and reference literature available online ?
PS, price is also an issue !

EMIF Toolkit create Memory Interface Connection problem

June 22, 2018, 6:42 am

≫ Next: Cyclone V FPGA-to-HPS Bridges design example bug?

≪ Previous: Which FPGA/CPLD dev-kit should I go for ?

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Hi all ,

I'm working on EMIF and i can't create connection with the EMIF tool kit to visualize the calibration report
i always get this error :

"Connection target /devices/1SG280HH(1S1|2S1|3S1)|..@1#3-11.4.1/(link)/JTAG/alt_sld_fab_0_alt_sld_fab_0_sldfabric.node_8/jtag_phy_0.jtag/master failed to execute the command. A response was not received from the connection target within the allowed time."



if i'm missing some thing can any one tell me ?
is there any solution ?'

Attached Images

• Screenshot from 2018-06-22 13-21-06.jpg (19.6 KB)