I've written a module to control the operation of an I2C bus where the SDA line is a bidirectional port. I've attempted to constrain it with these SDC commands:
where i2c_clk is a generated clock:
CLOCK_50 is the 50MHz input clock to the design, i2c:i2c_inst|i2c_clk is used because I instantiate the I2C module in a top level module.
The output delay seems to work fine, but I'm getting issues with the input delay. I'm getting the error messages "FPGA_I2C_SDAT could not be matched with a port" (even though it works fine for output) and "Argument <targets> is an empty collection". Additionally, when I check my unconstrained input ports TimeQuest gives "FPGA_I2C_SDAT" (i.e. exactly as I have it in the constraint). I thought it might be an error caused by specifying output and input delays on the same port, but if I comment out the output delay it still gives the same error for the input delay.
I noticed in Ryan Scoville's TimeQuest User Guide on page 114 that internal clocks should not be used to constrain IO ports. However, this clock is exported (or at least a combinational derivative of it that accounts for when SCL should be active and when it shouldn't be active according to the I2C standard) and synchronizes the components outside the FPGA. Furthermore, if I replace this with a virtual clock of the same period I get the same error, so it doesn't look like that's the issue.
If any part of this question is unclear I'd be happy to clarify/post more code. Thanks in advance.
Code:
set_output_delay -clock i2c_clk -min 0.0 [get_ports {FPGA_I2C_SDAT}]
set_output_delay -clock i2c_clk -max 0.0 [get_ports {FPGA_I2C_SDAT}]
set_input_delay -clock i2c_clk -max 0.0 [get_ports {FGPA_I2C_SDAT}]
set_input_delay -clock i2c_clk -min 0.0 [get_ports {FGPA_I2C_SDAT}]Code:
create_generated_clock -source [get_ports CLOCK_50] -divide_by 126 -name i2c_clk [get_nodes {i2c:i2c_inst|i2c_clk}]The output delay seems to work fine, but I'm getting issues with the input delay. I'm getting the error messages "FPGA_I2C_SDAT could not be matched with a port" (even though it works fine for output) and "Argument <targets> is an empty collection". Additionally, when I check my unconstrained input ports TimeQuest gives "FPGA_I2C_SDAT" (i.e. exactly as I have it in the constraint). I thought it might be an error caused by specifying output and input delays on the same port, but if I comment out the output delay it still gives the same error for the input delay.
I noticed in Ryan Scoville's TimeQuest User Guide on page 114 that internal clocks should not be used to constrain IO ports. However, this clock is exported (or at least a combinational derivative of it that accounts for when SCL should be active and when it shouldn't be active according to the I2C standard) and synchronizes the components outside the FPGA. Furthermore, if I replace this with a virtual clock of the same period I get the same error, so it doesn't look like that's the issue.
If any part of this question is unclear I'd be happy to clarify/post more code. Thanks in advance.