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Pio write data error

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Hi all,

I am using IOWR_ALTERA_AVALON_PIOS macros to write data onto pios. But when I am writing the data onto 1 pins, all the other pins are assigned the same value at the same time. Does anyone know why this happens? Thank you very much!

Epf10k30ri240-4n, epf10k50ri240-4n

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I need you expert opinion. I get this circuits from distributor, but I doubt in quality this product. On this product ink marking and other suspicious. In accordance with ADV0217, the laser marking changed ink in 2008, after this date,customers can receive either laser marked or ink-marked devices. When is the final date of transition to laser marking? I can not use an IC with a non-fixed type of marking in my final module and I can not always guess the IC with which marking you will put to me. Please say me what do you think about my question?
suspiciousI doubt the quality of this productdistributorexpert opinionexpert opinionexpert opinion

Kernel Panic programing fpga from Linux

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Hello Community,

I receive the following error when I want to program the fpga from Linux:

Code:

fpga_manager fpga0: writing fpga.rbf to Altera SOCFPGA FPGA Manager
Unable to handle kernel NULL pointer dereference at virtual address 00000008

The full kernel log is in attachment: kernel-log.txt
The device tree is in attachment: device-tree.txt
The kernel defconfig is in attachment: kernel-deconfig.txt
Device-tree overlay file is in attachment: dtso.txt

I hope u can help me. Thanks in advance.

I use buildroot 2018.05 to build the device-tree, the kernel and all the rest for a Linux Embedded device.

I tried the following kernel versions: rel_socfpga-4.9.78-ltsi_18.07.01_pr and rel_socfpga-4.16_18.06.02_pr from https://github.com/altera-opensource/linux-socfpga but both have the same error.
Attached Files

verilog program

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hello everyone,
i am working on electro-chemical sensor. i am working for detection of cardiac troponin I in blood sample. I have to make a physical electronic device. for that motive, i think i have to work on language for microcontroller like ardiuno. I have a little knowledge on verilog. I want to work on verilog for complition of this project. Can anyone help me to write a verilog program for electrochemical detection.

aocl list-devices : No devices attached for package:

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When i run "aocl list-devices" command what i get is following output

-bash-4.2$ aocl list-devices
--------------------------------------------------------------------
Warning:
No devices attached for package:
<.....>/hld/board/a10_ref
--------------------------------------------------------------------

Seems the device is not added properly. What could be the reason.
Due to this I am not able to program my PAC.

Verifying Configuration Memory after Programming

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I'm working on an application for a high EMI environment and need to constantly verify the configuration of an FPGA to ensure that the circuit isn't being damaged/altered by the noise. I know I can do it prior to programming the device, but how do I go about reading/verifying the configuration of a chip that's already been programmed? Is there a way to access the LUTs from the JTAG header? I don't need to know where the problem occurs, only whether something's been altered. A go/no go scenario, where any change causes me to halt the chip. If not JTAG, is there any other way for me to accomplish this?

Trouble using EPCS on Intel (Altera) DE10-standard

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I'm using the DE-10 standard Intel FPGA. I'm trying to get a simple program that blinks a single LED to run when the FPGA is booted. From my understanding of the manual, the process involves converting my .sof file to a .jic file and using the Quartus programmer to place the .jic file on the FPGA. My .sof file does correctly work and the LED blinks. Practically every guide and tutorial I've seen follow this process and seem to get successful results.
When I perform this process, Nothing seems to be saved into non-volatile memory. When I restart the board, all the LEDs are lit to their default brightness. When I initially start the program from the programmer, all of the LEDs go blank as if the contents have been erased. I'm not really sure where I can be going wrong.

I asked for help on another forum asked to make sure that I configured my devices to Active Serial x1. I did this, but the program is still not saving to flash.

For reference, I'm using Altera's manual (page 121)
and this youtube video
Any help or assistance will be greatly appreciated. Thank you.

TCL console path initialization

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I am trying to run commands in the Quartus 16.0 Tcl console window. Commands like quartus_map result in that the command name is invalid.

I am running on Windows and have edited the PATH variable to include C:\altera\16.0\quartus\bin64 which is where the executables are located on my machine. I am able to run the commands from the nios shell but from the Quartus GUI tcl console I get the above error. So I am unsure how to setup whatever initialization is done when Quartus is launched so that it can find these commands or pickup the Windows PATH environment variable

Thanks,
Dave

10GBase-R rx_ready not stable

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Good afternoon, colleagues.
I start 10GBase-R on Stratix V. The rx_ready status of the first 2-3 seconds is very unstable, then 0, then 1.
What could be the reason? I suspect because of this link does not appear

VHDL code error

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Hello,

I am trying to do Bit Error Rate Testor on my FPGA Altera Cyclone V board and SFP-HSMC. I am trying to send 3Gbps of data where as the maximum the transceiver or receiver can send or receive is 3.25Gbps. I am getting few errors which I am not able to figure out where the error exactly is. I request you to please let me know what changes do I need to make in the code.

Thanks a ton in advance.
Attached Images

multiple kernel in a .cl file

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I have a question about in appended single CL file case,
1、in followed CL file ,when only have clip_8b_kernel、ITransformOne_kernel、GetSSE_kernel and if put ITransformOne_kernel before GetSSE_kernel will get an error as followed if place them in the order of clip_8b_kernel、GetSSE_kernel、ITransformOne_kernel can compile successfully .
2、this CL file include multiple kernel and i find If compile any of these kernels separately have no error but the kernel of ITransform_C_kernel and ITransform_one_kernel Cannot exist simultaneously, if exist simultaneously it will have the error followed.


error content:
aoc: Linking with IP library ...
/build/swbuild/SJ/nightly/17.0/290/l64/p4/acl/llvm/include/acl/Analysis/LocalMemSizing.h(83) *******
Requested memsize for unavailable aspace


m_local_mem_size_per_workgroup.count(aspace) FAILED
0 libLLVM-3.0.so 0x00007f348ee2846f
1 libLLVM-3.0.so 0x00007f348ee2a3e2
2 libpthread.so.0 0x00007f348da905e0
3 libLLVM-3.0.so 0x00007f348f617ef9 acl::get_bits(llvm::Value const*, llvm::TargetData*, acl::LocalMemSizing*, bool, bool, bool) + 7289
4 libLLVM-3.0.so 0x00007f348e37a880 grif::Pass_AreaReport::add_private_var_resources() + 8800
5 libLLVM-3.0.so 0x00007f348e37c7e1 grif::Pass_AreaReport::runPass(grif::XNode*) + 913
6 libLLVM-3.0.so 0x00007f348e34c58a acl::DSDKGenerate::runOnModule(llvm::Module&) + 8010
7 libLLVM-3.0.so 0x00007f348f049fc1 llvm::MPPassManager::runOnModule(llvm::Module&) + 577
8 libLLVM-3.0.so 0x00007f348f04a16b llvm::PassManagerImpl::run(llvm::Module&) + 187
9 aocl-llc 0x000000000040be40 main + 5360
10 libc.so.6 0x00007f348ca9ec05 __libc_start_main + 245
11 aocl-llc 0x00000000004098e9
Stack dump:
0. Program arguments:
/home/****/inteldevstack/intelFPGA_pro/hld/linux64/bin/aocl-llc -march=griffin -board /home/****/inteldevstack/a10_gx_pac_ias_1_0_prq/opencl/opencl_bsp/hardware/pac_a10/board_spec.xml -dbg-info-enabled test.bc -o test.v
1. Running pass 'Generate DSDK netlist and HDL' on module 'test.bc'.
Error: Verilog generator FAILED.
Refer to test/test.log for details.

CL file:

typedef uchar uint8_t;
typedef short uint16_t;
typedef int uint32_t;
#define clip_8b_const_v_LEN 1
#define clip_8b_out_clip_8b_return_LEN 1
#define ITransformOne_in_ref_LEN 200
#define ITransformOne_in_in_LEN 200
#define ITransformOne_inout_dst_LEN 200
#define GetSSE_in_a_LEN 200
#define GetSSE_in_b_LEN 200
#define GetSSE_const_w_LEN 1
#define GetSSE_const_h_LEN 1
#define GetSSE_out_GetSSE_return_LEN 1
#define ITransform_C_in_ref_LEN 200
#define ITransform_C_in_in_LEN 200
#define ITransform_C_inout_dst_LEN 200
#define ITransform_C_const_do_two_LEN 1
/****** VP8Calc -- VP8Transform *************************************************/
#define WEBP_INLINE inline
#define BPS 32


static WEBP_INLINE uchar clip_8b(int v) {
return (!(v & ~0xff)) ? v : (v < 0) ? 0 : 255;
}


#define STORE(x, y, v) \
dst[(x) + (y) * BPS] = clip_8b(ref[(x) + (y) * BPS] + ((v) >> 3))
#define kC1 (20091 + (1 << 16)) // DF: NEW
#define kC2 35468 // DF: NEW
#define MUL(a, b) (((a) * (b)) >> 16)


static WEBP_INLINE void ITransformOne(const uint8_t * ref, const uint16_t* in,
uint8_t* dst) {
int C[4 * 4], *tmp;
int i;
tmp = C;
for (i = 0; i < 4; ++i) { // vertical pass
const int a = in[0] + in[8];
const int b = in[0] - in[8];
const int c = MUL(in[4], kC2) - MUL(in[12], kC1);
const int d = MUL(in[4], kC1) + MUL(in[12], kC2);
tmp[0] = a + d;
tmp[1] = b + c;
tmp[2] = b - c;
tmp[3] = a - d;
tmp += 4;
in++;
}


tmp = C;
for (i = 0; i < 4; ++i) { // horizontal pass
const int dc = tmp[0] + 4;
const int a = dc + tmp[8];
const int b = dc - tmp[8];
const int c = MUL(tmp[4], kC2) - MUL(tmp[12], kC1);
const int d = MUL(tmp[4], kC1) + MUL(tmp[12], kC2);
STORE(0, i, a + d);
STORE(1, i, b + c);
STORE(2, i, b - c);
STORE(3, i, a - d);
tmp++;
}
}


void ITransform_C(const uint8_t * ref,const uint16_t * in,uint8_t * dst, int do_two) {
ITransformOne(ref, in, dst);
if (do_two) {
ITransformOne(ref+ 4, in + 16, dst+ 4);
}


}


static WEBP_INLINE int GetSSE(const uint8_t* a, const uint8_t* b,
int w, int h) {
int count = 0;
int y, x;
for (y = 0; y < h; ++y) {
// DF: TBC, may need to unroll this
for (x = 0; x < w; ++x) {
const int diff = (int)a[x] - b[x];
count += diff * diff;
}
a += BPS;
b += BPS;
}
return count;
}


__kernel void clip_8b_kernel( int v,__global uchar* restrict clip_8b_return){
printf("start func:clip_8b\n");
uchar clip_8b_return_[clip_8b_out_clip_8b_return_LEN];
clip_8b_return[0] = clip_8b(v);
for(int i = 0;i<clip_8b_out_clip_8b_return_LEN;i++){
clip_8b_return[i] = clip_8b_return_[i];
}
}
__kernel void ITransformOne_kernel(__global uint8_t * restrict ref,__global uint16_t* restrict in,__global uint8_t* restrict dst){
printf("start func:ITransformOne\n");
uint8_t ref_[ITransformOne_in_ref_LEN];
uint16_t in_[ITransformOne_in_in_LEN];
uint8_t dst_[ITransformOne_inout_dst_LEN];
for(int i = 0;i<ITransformOne_in_ref_LEN;i++){
ref_[i] = ref[i];
}
for(int i = 0;i<ITransformOne_in_in_LEN;i++){
in_[i] = in[i];
}
for(int i = 0;i<ITransformOne_inout_dst_LEN;i++){
dst_[i] = dst[i];
}
ITransformOne(ref_,in_,dst_);
for(int i = 0;i<ITransformOne_inout_dst_LEN;i++){
dst[i] = dst_[i];
}
}
__kernel void GetSSE_kernel(__global uint8_t* restrict a,__global uint8_t* restrict b, int w, int h,__global int* restrict GetSSE_return){
printf("start func:GetSSE\n");
uint8_t a_[GetSSE_in_a_LEN];
uint8_t b_[GetSSE_in_b_LEN];
int GetSSE_return_[GetSSE_out_GetSSE_return_LEN];
for(int i = 0;i<GetSSE_in_a_LEN;i++){
a_[i] = a[i];
}
for(int i = 0;i<GetSSE_in_b_LEN;i++){
b_[i] = b[i];
}
GetSSE_return[0] = GetSSE(a_,b_,w,h);
for(int i = 0;i<GetSSE_out_GetSSE_return_LEN;i++){
GetSSE_return[i] = GetSSE_return_[i];
}
}
__kernel void ITransform_C_kernel(__global uint8_t * restrict ref,__global uint16_t * restrict in,__global uint8_t * restrict dst, int do_two){
printf("start func:ITransform_C\n");
uint8_t ref_[ITransform_C_in_ref_LEN];
uint16_t in_[ITransform_C_in_in_LEN];
uint8_t dst_[ITransform_C_inout_dst_LEN];
for(int i = 0;i<ITransform_C_in_ref_LEN;i++){
ref_[i] = ref[i];
}
for(int i = 0;i<ITransform_C_in_in_LEN;i++){
in_[i] = in[i];
}
for(int i = 0;i<ITransform_C_inout_dst_LEN;i++){
dst_[i] = dst[i];
}
ITransform_C(ref_,in_,dst_,do_two);
for(int i = 0;i<ITransform_C_inout_dst_LEN;i++){
dst[i] = dst_[i];
}
}






Who can help me? Thanks in advance.

8 MHz clock from 100 MHz

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I am generating 8 MHz clock by scaling down the 100 MHz clock. The design I have implemented simulates well but when loaded on MAX-10 and observed using Signal Tap II logic analyzer the clock signal behaves completely different. Its period and duty cycle varies across the waveform.<br><img src="https://alteraforum.com/forum/attachment.php?attachmentid=15822&amp;stc=1" attachmentid="15822" alt="Simulation" id="vbattach_15822" class="previewthumb"><br><img src="https://alteraforum.com/forum/attachment.php?attachmentid=15823&amp;stc=1" attachmentid="15823" alt="As observed on Logic Analyzer" id="vbattach_15823" class="previewthumb"> Any guess why its behaves like this?

The design is based on a counter in verilog:

Code:

always @ (clk)
begin
    if (clk_counter < 5'b01011)
    begin
        clk_counter    <=    clk_counter + 5'b00001;
    end
    else if (clk_counter == 5'b01011)
    begin
        SCLK    <=    1'b1;
        clk_counter    <=    clk_counter + 5'b00001;
    end
    else if ((clk_counter > 5'b01011) && (clk_counter < 5'b11001))
    begin
        clk_counter    <=    clk_counter + 5'b00001;
    end
    else if (clk_counter >= 5'b11001)
    begin
        SCLK    <= 1'b0;
        clk_counter    <=    5'b00000;
    end
end

Fft core generation stuck

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Hi all,

When I am using FFT core mega-wizard in Quartus 13.1, the toolbench stuck at this screen. And I have tried the solution of killing quartus-map in task manager, which this thing doesn't exist in my task manager. So, if anyone have any idea, please give me some help! Thank you very much! P.S: My operating system is win10, and cpu is Core M.
Attached Images

can't see enough FMAX

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hello

I create one FPGA project with CycloneV( 5CGXFC9E6F35C7 ).
it has 80 pairs of LVDS inputs as DDRIO input.

when I compile the project, it says FMAX is 103MHz that is too slower than I expected.
I need 300MHz.

I tried to compile each 8bits LVDS inputs independently.
then I found that some of them is 260MHz FMAX ( that still not enough by the way. )
the other hand, some other is 103MHz FMAX.

why LVDS input has different FMAX?
I mean this big difference.

do I miss something?

thank you.

Using SPI core Stratix IV

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Hello

I want to use a Stratix IV dev kit to control an SPI device( it's a frequency generator board and it supports mini USB connection)! since the FPGA board only supports HSMC/PCI Express interfaces i want to use an PCIE to USB converter board to translate the data from PCIE to USB 3. My suggested configuration : Avalon-ST SPI core -> PCIE core -> PCIE to USB adapter -> SPI device through USB

I have not been able to find a demo or similar setup. Anyone knows how to interconnect Avalon-ST SPI Core to PCIE IP compiler in block diagram? or any other possible way to connect my SPI device to the FPGA board?


Thanks for hints,

Regards,

Stratix 10 Package Mechanical Drawings?

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I've searched pretty thoroughly the Intel / Altera website and all the documentation the Stratix 10 and I can't seem to find the mechanical drawings for the packages. Has anyone run across them? I need them so I can locate a socket for my development work. I'm primarily interested in the HF55 (largest 55 x 55 mm2) package.

Any input would be appreciated, thanks,
Todd

DDR3 hard memory controller usage issue

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Hello all I have implemented a hard memory controller on the Altera Cylcone V SOC development board.
The board calibrates successfully but when I write some thing to address '0' and try to read it back, I only see zeros. Read data valid does go high though.
I have attached signal tap screen caps. The first shows the write and read operation. The second shows read data valid going high but no valid data on readdata.

I have simulated the full design and it works correctly.

Any suggestions?

Thanks!

Attached Images

Altera Frame Reader Buffer Padding

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I've been working on the Altera FrameReader IP core and have created a reference design for the Cyclone V SOC. I have a NIOS based software application that is using this design and displaying images on the OLED. Everything works well. Now for a special reason, I need to pad my frame buffer with extra memory(50 pixels in either direction). The original frame buffer is 1280*960 and I want to convert it into the buffer of 1380*1060 and start the frame reader from the X=50, Y=50 of the 1380*1060 buffer. In this way, the buffer would be equally padded 50 pixels in either directions.

However, I'm unable to get it working because the altera frame reader IP reads contiguous memory and thus, the memory that I consider padded memory is used by the frame reader and displayed on the OLED. Is there any way around this problem ? May be a configuration register in the Frame reader that allows me to do this.

Any help would be appreciated.

Regards,

MAX10 initialization

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Max10 devices don't have INIT_DONE pin to indicate initialization finished, How can I know the device goes into user mode?

A question on Addressing of peripherals in Qsys

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Hi,

Background: I have generated a Qsys system. There is a 8 bit Pio in the design. After completion of the design, I assigned system address automatically.

The situation is: system is assigning an address space from x11020 to x1102f to this PIO, which makes 16 different addresses.

And the question is: Why for a single 8 bit PIO, the system is assigning 16 addresses? why? Isn't that a wastage of resources? or something there which I am missing?

Thanks in advance.

Cheers
Tahir
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