SDC problem

hi,
My requriement is that:
There are two input signal, In_a, In_b, these two signals will be connected to clock and data (llike I2C). two output signal, Out_clock, Out_data.
Because the In_a could connect to clock or data, so i need write a module to identify which one(clock or data) will connet to In_a, then re-arrange the order and output the correct signal , i.e. Out_clock or Out_data.

the code is like this:

module Switch(input wire In_a, input wire In_b, input wire S, output wire Out_clock, output wire Out_data)
begin
assign Out_clock = S ? In_a : In_b;
assign Out_data = S ? In_b : In_a;
end

if S is connected to external pin, the maxmum frequency is 200Mhz.

if i write a module to generate control signal S by In_a and In_b, for example like this
module Identify( input wire In_a, input wire In_b, out reg S)
begin
//some statistic code to indetinfy .......
end

the maximu frequency is 30Mhz.

The problem is:
I want the signals from In_a and In_b to Out_clock and Out_data can run at 100Mhz. the module Identify will influence the frequency(tsu). I want to write a SDC file to optimize the maximu speed.
the Identify moule just generate signal S to pick up which one is clock. if the S is ready, it is latched and needn't changed again . the data can be discarded before the S is generated.

So, how can i do this ?

will set_max_delay -from -to affect?

best ...