Hi,
I am facing an issue while using byte enable memory. My memory is
This RAM is written only once, 2 bytes at a time, during run time and then I read it for a long period. So I used total 16 clock cycles to fill complete. I have verified my logic in simulation but after synthesis and debugging using SignalTap I found that the RAM outputs are always zero. Input behavior is somewhat similar to the scenario i tested in simulation. Hope u may got what i am trying to do. I have checked the synthesis warning and I didn't found anything related to this RAM.
Please try to correct me where did I make the violation of rule(s) related to memory usage.
Thanks In Advance
I am facing an issue while using byte enable memory. My memory is
- 128-bit wide
- dual clocked
- read clock runs at 400MHz while write clock runs at 200MHz
- Its depth is only 2 i.e. read and write addresses are 1-bit wide only
- Forced to map on M9Ks
- Read port is connected to 200MHz clock (instead of making a toggling signal using 400MHz clock)
This RAM is written only once, 2 bytes at a time, during run time and then I read it for a long period. So I used total 16 clock cycles to fill complete. I have verified my logic in simulation but after synthesis and debugging using SignalTap I found that the RAM outputs are always zero. Input behavior is somewhat similar to the scenario i tested in simulation. Hope u may got what i am trying to do. I have checked the synthesis warning and I didn't found anything related to this RAM.
Please try to correct me where did I make the violation of rule(s) related to memory usage.
Thanks In Advance