run synthesis/routing on a cloud server?
I am developing an educational FPGA board that runs on arduino. It is for classroom and hobbyist use. It would not be practical for each student to download and run the dev tools on their laptops. We...
View Articleemulator for Windows
I have installed "Altera pro Quartus" and visual Studio. How do I install Emulator? I am looking at the setclenv.bat from Training material and it is setting to a board at \hd\board\c5soc and I don't...
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QSYS 1st timer -- JTAG to Avalon Master Bridge fails in System Console
Newer user of QSYS and System console here. I have a JTAG-Avalon master connected as in qsys interconnect picture below. When I try to open service to the only master that is recognized (named phy_0)...
View ArticleRemote Configuration of FPGA Flash via FPGA
Is it acceptable to use a cyclone v user I/O pins to program the flash memory containing configuration for the cyclone v. This would be muxed in after power-up/configuration with the DCLK and other...
View Articleresizing sfixed number
i want to resize a sfixed number of size(9 downto -6) to sfixed/signed of size (9 downto 0): here's the code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; library ieee_proposed; use...
View ArticleUsing DE2-115 for Labs designed for DE2
Hi, We have some DE2 boards that will be replaced with DE2-115 boards. We have labs that were designed for the DE2 board and i am wondering how difficult it will be to convert those labs from DC2 to...
View ArticleCyclone V PCIe hard IP? Megafunction required??
Hello, quick question for everyone. I've been looking over the documentation on the Cyclone V PCIe hard IP and not sure if you need to buy a Megafunction to implement a PCIe link on the Cyclone V? The...
View ArticleHow do I will solidify the nios ii program in fpga
How do I will solidify the nios ii program in fpga. Can you give me a tutorial.
View ArticleSimulation of IP core in quartus 2 version15
I am not able to simulate the IPcores generated using the IP cores listed on the quartus2 version 15. only the .qip file is generated..sip is not found. when i used qsys, .sip file is generated and i...
View Articleethernet ip
can i implement Triple Speed ethernet TSE core in max10 (10 M 16) device???? Resmi
View ArticleAltera opencl, Diff usage of Processors when using parallel compilation of...
I am using "Hello world" of example designs offered by Altera Opencl. (https://www.altera.com/products/desi...esign-examples) I use the "aoc" command and get the .aocx file. but I have a confusion: in...
View ArticleUse Avalon IP cores in Quartus II (not Qsys)
Dear all, I'd like to add an Avalon ST IP core to my Quartus II project but the IP core is not available in the IP catalog. It is available in the Qsys IP catalog, though. Specifically, I'd like to...
View ArticleHPS Timing Warnings
Hello SOC Specialists, currently I work on a Cyclone V with HPS. Qsys generates a few sdc-files. My problem is, ... a lot of constraints are ignored. If I correct the signal names within...
View Articletriple speed ethernet example for MAC10 with quartus 15.1
I have downloaded and complied the TSE based solution on quartus ver 15.1. I downloaded the solution from : https://cloud.altera.com/devstore/pl...ethernet-uart/ The compilation is fine but I see...
View ArticleHow does the kernel determine the resource flags of a device node in a device...
I'm developing a devicedriver in a socfpga-linux provided by SoC EDS 15.1.1.60 for a customFPGA based PCIe Root Complex design on Altera Arria 10 board. I'mtaking pcie-altera.c for reference. When my...
View ArticleStratix II GX PCI Express Development Kit License Issue
Hi All, I have recently inherited a "PCI Express Development Board, Stratix II GX Edition" which uses a "Stratix II GX EP2SGX90F1508C3" FPGA. I looked up the Quartus II compatibility table and...
View ArticleCreating a terminal to control Nios-II to send commands to SPI slave
To ease testing of slave devices e.g memory devices, ADCs e.t.c is it possible to create an application where one has a terminal window open on PC from which one can write specific words to an SPI...
View Articletransmit raw file to a flash device connected to altera device
provided that I have a raw data file describing exactly how data must fit into a flash device connected to an altera device, is there an altera-approved method to transfer this file into flash device...
View ArticleUsing UART at arbitrary BAUD Rate
I am using QSYS on the MAX10. I am interfacing to another board over an LVDS Physical Layer using a UART. The data rate is 80 MHZ. I am planning on oversampling at a clock rate 4x the data rate ie 320...
View ArticleBlack Box QSYS Components
I am starting my first QSYS design. I will have to create some of my own components. I would like to create them first as black boxes so that I can do a block diagram of the system, and then go back...
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