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New Development Boards by Startup
Hi All, My company is releasing two Cyclone IV E Dev boards, and a module system. I wanted to put links he for your information. *Disclosure* Yes, I'm flogging a product, but I'm hoping to get feedback...
View ArticleProgram EPC1 with usb blaster and pof file
Hi, i want to burn an old epc1pi8 device this is what i got: an old pof file for epc1 device screen: i.imgur*com/uCZcGUH.png usb blaster some skills and some components to build up some hardware. is...
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SGMII interface - MDIO 0 and MDIO 1 space access??
Hi all, We are using a Marvell Phy IC with the altera TSE MAC IP in SGMII interface. According to the datasheet, we feel the MDIO 0 and MDIO 1 space access is as shown in the block diagram MDIO.jpg So...
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Is there a clock recovery Mechanism in TSE MAC?
Hi all, We are using a cyclone IV fpga with a Marvell PHY through an SGMII interface. As per the Marvell datasheet BLOCK1.JPG the interface for SGMII should be as explained in this diagram for MACs...
View ArticleTerasic DE5 OpenCL support
Hi, We obtained a Terasic DE5 board through the Altera University Program, with the intention to use it for OpenCL development. It seems, however, that there was some miscommunication as the DE5 is not...
View ArticleSubsystem Builder in DSPBuilder Advanced Blockset
Hi, I am using DSPBuilder Version 12.0. In the standard blockset, there is a Subsystem Builder block, using which we can generate a black-box from the existing HDL file. Is there any option in Advanced...
View ArticleAltera PLL v13.0 in MegaWizard Plug-In Manager
I'm using Quartus II 64-Bit Version 13.0.1 Web Edition and the Altera PLL v13.0 is not available in the MegaWizard Plug-In Manager. How do I get my hands on it? Thanks
View ArticleSimulating custom DDR controller with ALTMEMPHY using ModelSim-Altera Starter...
I'm designing a custom DDR controller using one instance of the ALTMEMPHY generated with the MegaWizard Plug-in Manager. The simulation files generated using Quartus II version 11.1sp2 or 13.0sp1 are...
View ArticleFFT Megacore Error
Hi, when i try to generate the VHDL code using the FFT megacore function, I get an error. The first few times a ran the megafunction the generation was successful. The parameter are not specific for...
View ArticleSynthesis error in VHDL process
Hi, I am trying to implement clock synchronizer and clock divider in the following piece of VHDL code. The clocks(clk_rx and clk_tx) should synchronize at the rising and falling edges of 'RX' signal on...
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Function of MSEL pins in FPGA
Dear sir, I would like to know, the function of MSEL[2:0] pins on Cyclone-IV. What will they decide ? Will they decide the mode in which the FPGA is getting configured ? Or the mode in which the EEPROM...
View ArticleOpenCL SDK on Ubuntu
Hi,The OpenCL SDK Release page says that Redhat EL 5.6 is the only supported Linux distribution. We have a server with 32G RAM running Ubuntu 12.04.I am just curious to know if OpenCL SDK will run fine...
View ArticleQuartus-Cannot load library error (tsm_ddrtcl.dll)
Hello, I`ve been getting this error below every time when I try to open quartus.I `ve reinstalled the program a few times.It did not solve the problem.When I open the program once after the...
View ArticleDisplay of different characters on the 7 segment display
Hi, please I am a beginner in Verilog and Altera FPGAs and I want to implement a lab on FPGA based PID controllers for DC Motor position control. Please I want to be able to display the P and I gains...
View ArticleuCLinux SGMII and SFP modules
Hi All, We have a custom Cyclone IV board with an SFP interfaced to the FPGA via SGMII on a standard Altera TSE. We also have an opencores i2c bus to control the moddef pins. We have a uClinux build...
View ArticleNodes missing in signaltap
Hello, I've got 2 sdram controllers connected to a NIOS II system. These sdram-controllers are exactly the same (they address only different address-spaces) but when I want to display some signals in...
View ArticleCyclone V + ALTLVDS + Multi-channel ADC
Dear all, I am trying to fit a design in a Cyclone V FPGA (E series, A7, FBGA 484 pins). The FPGA receives 16 LVDS channels at 875 Mbps each. The data comes from a LTM9011-14 ADC from Linear...
View ArticleTopic: how shift in(16 bit) and shift out(1 bit at a time)
Topic: how shift in(16 bit) and shift out(1 bit at a time) Example:shiftin[15..0] and shiftout[0] How to edit the RAM- based shift register(Altshift_taps) megafunction to meet my requirement Currently...
View ArticleCyclone V SoC - Shared Memory Controller
Hi @all, I have a problem generating a Design with connection from FPGA to the HPS-Memorycontroller. I set up a QSYS-System with the connections and now try to get data from this Memory. I have seen...
View ArticleUnable to do PCIe example design simulation in ModelSim PE
I followed the instructions given in the Cyclone V PCIe userguide and generated the example design. I than used msim_setup.tcl in ModelSim-Altera and was successful in doing the simulation. I than did...
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